Searched refs:base (Results 51 - 75 of 1028) sorted by relevance

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/u-boot/drivers/i2c/
H A Drcar_i2c.c65 void __iomem *base; member in struct:rcar_i2c_priv
79 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
82 writel(0, priv->base + RCAR_I2C_ICSSR);
83 writel(0, priv->base + RCAR_I2C_ICMSR);
84 writel(0, priv->base + RCAR_I2C_ICMCR);
99 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
101 writel(mcra, priv->base + RCAR_I2C_ICMCR);
107 writel(mcra, priv->base + RCAR_I2C_ICMCR);
109 writel(mcr, priv->base + RCAR_I2C_ICMCR);
111 writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base
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H A Dlpc32xx_i2c.c53 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base, argument
72 writel(half_period, &base->clk_hi);
73 writel(half_period, &base->clk_lo);
78 static void __i2c_init(struct lpc32xx_i2c_base *base, argument
82 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
84 __i2c_set_bus_speed(base, requested_speed, chip);
88 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev) argument
93 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
94 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
98 &base
110 __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr, int alen, u8 *data, int length) argument
177 __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr, int alen, u8 *data, int length) argument
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H A Docteon_i2c.c179 * @base: Base address of i2c registers
183 void __iomem *base; member in struct:octeon_twsi
188 static void twsi_unblock(void *base);
189 static int twsi_stop(void *base);
250 * @base Base address of i2c registers
254 static u64 twsi_write_sw(void __iomem *base, u64 val) argument
261 debug("%s(%p, 0x%llx)\n", __func__, base, val);
262 writeq(val, base + TWSI_SW_TWSI);
264 val = readq(base + TWSI_SW_TWSI);
275 * @base Bas
279 twsi_read_sw(void __iomem *base, u64 val) argument
305 twsi_write_ctl(void __iomem *base, u8 data) argument
321 twsi_read_ctl(void __iomem *base) argument
339 twsi_read_status(void __iomem *base) argument
355 twsi_wait(void __iomem *base) argument
375 twsi_start_unstick(void __iomem *base) argument
389 twsi_start(void __iomem *base) argument
420 twsi_stop(void __iomem *base) argument
444 twsi_write_data(void __iomem *base, u8 slave_addr, u8 *buffer, unsigned int length) argument
515 twsi_unblock(void __iomem *base) argument
542 twsi_read_data(void __iomem *base, u8 slave_addr, u8 *buffer, unsigned int length) argument
656 twsi_init(void __iomem *base, int slaveaddr) argument
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/u-boot/drivers/phy/qcom/
H A Dphy-qcom-snps-femto-v2.c61 void __iomem *base; member in struct:qcom_snps_hsphy
74 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, argument
79 reg = readl_relaxed(base + offset);
83 writel_relaxed(reg, base + offset);
86 readl_relaxed(base + offset);
93 qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0,
96 qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR,
98 qcom_snps_hsphy_write_mask(priv->base,
100 qcom_snps_hsphy_write_mask(priv->base,
103 qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_REFCLK_CTR
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/u-boot/drivers/spi/
H A Dgxp_spi.c33 void __iomem *base; member in struct:gxp_spi_priv
42 value = readb(priv->base + OFFSET_SPIMCTRL);
44 writeb(0x55, priv->base + OFFSET_SPICMD);
45 writeb(0xaa, priv->base + OFFSET_SPICMD);
51 writeb(value, priv->base + OFFSET_SPIMCTRL);
84 writeb(uchar_out[0], priv->base + OFFSET_SPICMD);
87 value = readl(priv->base + OFFSET_SPIMCFG);
95 writel(addr, priv->base + OFFSET_SPIADDR);
100 writel(0, priv->base + OFFSET_SPIADDR);
113 writel(value, priv->base
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/u-boot/drivers/serial/
H A Dserial_bcm6345.c86 void __iomem *base; member in struct:bcm6345_serial_priv
91 static void bcm6345_serial_enable(void __iomem *base) argument
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
98 static void bcm6345_serial_disable(void __iomem *base) argument
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
105 static void bcm6345_serial_flush(void __iomem *base) argument
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
112 readl(base + UART_FIFO_REG);
115 static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) argument
120 bcm6345_serial_disable(base);
271 void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); local
276 wait_xfered(void __iomem *base) argument
287 void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); local
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/u-boot/arch/arm/mach-mvebu/
H A Dmbus.c113 static void mvebu_mbus_read_window(int win, int *enabled, u64 *base, argument
128 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
129 *base |= (basereg & WIN_BASE_LOW);
173 * Checks whether the given (base, base+size) area doesn't overlap an
176 static int mvebu_mbus_window_conflicts(phys_addr_t base, size_t size, argument
179 u64 end = (u64)base + size;
201 if ((u64)base < wend && end > wbase)
214 static int mvebu_mbus_find_window(phys_addr_t base, size_t size) argument
230 if (base
237 mvebu_mbus_setup_window(int win, phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) argument
264 mvebu_mbus_alloc_window(phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) argument
325 u32 base = readl((void __iomem *)MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); local
361 mvebu_mbus_add_window_remap_by_id(unsigned int target, unsigned int attribute, phys_addr_t base, size_t size, phys_addr_t remap) argument
375 mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, phys_addr_t base, size_t size) argument
382 mvebu_mbus_del_window(phys_addr_t base, size_t size) argument
395 mvebu_mbus_get_lowest_base(phys_addr_t *base) argument
420 phys_addr_t base; local
442 mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr) argument
485 u32 base, size; local
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/u-boot/drivers/timer/
H A Dmchp-pit64b-timer.c27 void __iomem *base; member in struct:mchp_pit64b_priv
34 u32 lsb = readl(priv->base + MCHP_PIT64B_TLSBR);
35 u32 msb = readl(priv->base + MCHP_PIT64B_TMSBR);
48 priv->base = dev_read_addr_ptr(dev);
49 if (IS_ERR(priv->base))
50 return PTR_ERR(priv->base);
67 writel(MCHP_PIT64B_CR_SWRST, priv->base + MCHP_PIT64B_CR);
73 writel((15 << 8) | MCHP_PIT64B_MR_CONT, priv->base + MCHP_PIT64B_MR);
80 writel(~0UL, priv->base + MCHP_PIT64B_MSB_PR);
81 writel(~0UL, priv->base
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H A Dgxp-timer.c19 void __iomem *base; member in struct:gxp_timer_priv
27 val = readl(priv->base + USTIMEHI);
28 val = (val << 32) | readl(priv->base + USTIMELO);
38 priv->base = dev_read_addr_ptr(dev);
39 if (!priv->base)
H A Dstarfive-timer.c26 void __iomem *base; member in struct:starfive_timer_priv
35 return priv->timer_size - readl(priv->base + STF_TIMER_VALUE);
50 priv->base = dev_read_addr_ptr(dev);
51 if (!priv->base)
55 priv->base = priv->base + (0x40 * timer_channel);
71 writel(0, priv->base + STF_TIMER_INT_MASK);
74 writel(1, priv->base + STF_TIMER_CTL);
77 writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
79 writel(1, priv->base
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/u-boot/drivers/cache/
H A Dcache-ncore.c43 #define CCU_DIR_REG_ADDR(base, reg, dir) \
44 ((base) + (reg) + ((dir) * DIR_REG_SZ))
53 static void ncore_ccu_init_dirs(void __iomem *base) argument
61 num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
63 CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
70 writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
76 CCU_DIR_REG_ADDR(base,
85 clrbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
91 static void ncore_ccu_init_coh_agent(void __iomem *base) argument
100 CSUIDR_NUMCAIUS_GET(readl(base
127 ocram_bypass_firewall(void __iomem *base) argument
139 void __iomem *base; local
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/u-boot/drivers/pci/
H A Dpcie_brcmstb.c136 * @base: Base address of memory mapped IO registers of the controller
142 void __iomem *base; member in struct:brcm_pcie
184 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
199 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
224 *paddress = pcie->base + offset;
235 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
236 *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
284 * @base: Pointer to the PCIe controller IO registers
292 static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port, argument
299 writel(addr, base
319 brcm_pcie_mdio_write(void __iomem *base, unsigned int port, unsigned int regad, u16 wrdata) argument
339 brcm_pcie_set_ssc(void __iomem *base) argument
394 void __iomem *base = pcie->base; local
435 void __iomem *base = pcie->base; local
596 void __iomem *base = pcie->base; local
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/u-boot/lib/
H A Dlmb.c25 unsigned long long base, size, end; local
32 base = rgn->region[i].base;
34 end = base + size - 1;
38 name, i, base, end, size, flags);
79 phys_addr_t base1 = rgn->region[r1].base;
81 phys_addr_t base2 = rgn->region[r2].base;
89 phys_addr_t base1 = rgn->region[r1].base;
91 phys_addr_t base2 = rgn->region[r2].base;
101 rgn->region[i].base
247 lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, phys_size_t size, void *fdt_blob) argument
256 lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, phys_size_t size, enum lmb_flags flags) argument
346 lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) argument
353 lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size) argument
360 lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) argument
410 lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, phys_size_t size, enum lmb_flags flags) argument
418 lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) argument
423 lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) argument
464 phys_addr_t base = 0; local
506 lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size) argument
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H A Daddr_map.c16 u64 base, upper, addr; local
22 base = (u64)(address_map[i].vaddr);
23 upper = (u64)(address_map[i].size) + base - 1;
25 if (addr >= base && addr <= upper) {
38 phys_addr_t base, upper; local
43 base = address_map[i].paddr;
44 upper = address_map[i].size + base - 1;
46 if (paddr >= base && paddr <= upper) {
H A Dstrto.c28 /* Only select octal if we don't have a base */
58 ulong simple_strtoul(const char *cp, char **endp, uint base) argument
63 cp = _parse_integer_fixup_radix(cp, &base);
65 while (value = decode_digit(*cp), value < base) {
66 result = result * base + value;
86 int strict_strtoul(const char *cp, unsigned int base, unsigned long *res) argument
97 val = simple_strtoul(cp, &tail, base);
110 long simple_strtol(const char *cp, char **endp, unsigned int base) argument
113 return -simple_strtoul(cp + 1, endp, base);
115 return simple_strtoul(cp, endp, base);
118 ustrtoul(const char *cp, char **endp, unsigned int base) argument
139 ustrtoull(const char *cp, char **endp, unsigned int base) argument
160 simple_strtoull(const char *cp, char **endp, unsigned int base) argument
179 simple_strtoll(const char *cp, char **endp, unsigned int base) argument
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/u-boot/fs/squashfs/
H A Dsqfs_dir.c32 struct squashfs_base_inode *base = dir_i; local
38 switch (get_unaligned_le16(&base->inode_type)) {
40 dir = (struct squashfs_dir_inode *)base;
45 ldir = (struct squashfs_ldir_inode *)base;
72 struct squashfs_base_inode *base = dir_i; local
77 switch (get_unaligned_le16(&base->inode_type)) {
79 dir = (struct squashfs_dir_inode *)base;
83 ldir = (struct squashfs_ldir_inode *)base;
/u-boot/arch/arm/mach-nexell/
H A Dtimer.c61 static inline void timer_clock(void __iomem *base, int ch, int mux, int scl) argument
63 u32 val = readl(base + REG_TCFG0) & ~(0xFF << TCFG0_BIT_CH(ch));
65 writel(val | ((scl - 1) << TCFG0_BIT_CH(ch)), base + REG_TCFG0);
66 val = readl(base + REG_TCFG1) & ~(0xF << TCFG1_BIT_CH(ch));
67 writel(val | (mux << TCFG1_BIT_CH(ch)), base + REG_TCFG1);
70 static inline void timer_count(void __iomem *base, int ch, unsigned int cnt) argument
72 writel((cnt - 1), base + REG_TCNTB0 + (TIMER_TCNT_OFFS * ch));
73 writel((cnt - 1), base + REG_TCMPB0 + (TIMER_TCNT_OFFS * ch));
76 static inline void timer_start(void __iomem *base, int ch) argument
79 u32 val = readl(base
92 timer_stop(void __iomem *base, int ch) argument
103 timer_read(void __iomem *base, int ch) argument
120 void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER; local
164 get_timer(unsigned long base) argument
181 void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER; local
193 void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER; local
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/u-boot/common/init/
H A Dboard_init.c28 __weak void board_init_f_init_stack_protection_addr(ulong base) argument
33 gd->start_addr_sp = base;
98 * Actual reservation was done by the caller; the locations from base
99 * to base+size-1 (where 'size' is the value returned by the allocation
107 * this initialization function, the global data MUST be placed at base.
124 * an incrementation line of the form 'base += <some size>'. The last of
125 * these incrementations seems useless, as base will not be used any
127 * this increment will be essential as it will give base right value for
130 * and remove the last base incrementation, therefore leaving that last
134 void board_init_f_init_reserve(ulong base) argument
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/u-boot/arch/arm/mach-imx/
H A Diomux-v3.c16 static void *base = (void *)IOMUXC_BASE_ADDR; variable
46 base = (void *)IOMUXC_LPSR_BASE_ADDR;
55 base = (void *)IOMUXC_SNVS_BASE_ADDR;
63 __raw_writel(mux_mode, base + mux_ctrl_ofs);
66 __raw_writel(sel_input, base + sel_input_ofs);
71 base + pad_ctrl_ofs);
74 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
77 clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
83 base = (void *)IOMUXC_BASE_ADDR;
114 reg = readl(base
[all...]
/u-boot/drivers/virtio/
H A Dvirtio_mmio.c26 void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; local
36 ptr[i] = readb(base + offset + i);
43 b = readb(base + offset);
47 w = cpu_to_le16(readw(base + offset));
51 l = cpu_to_le32(readl(base + offset));
55 l = cpu_to_le32(readl(base + offset));
57 l = cpu_to_le32(readl(base + offset + sizeof(l)));
71 void __iomem *base = priv->base local
[all...]
/u-boot/include/linux/
H A Dmbus.h23 * The base address, size, and MBUS attribute ID for each
31 u32 base; member in struct:mbus_dram_target_info::mbus_dram_window
55 phys_addr_t base, size_t size,
58 phys_addr_t base, size_t size);
59 int mvebu_mbus_del_window(phys_addr_t base, size_t size);
60 int mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr);
/u-boot/drivers/gpio/
H A Dqe_gpio.c21 /* The bank's register base in memory */
22 struct gpio_n __iomem *base; member in struct:qe_gpio_data
40 struct gpio_n __iomem *base = data->base; local
44 clrsetbits_be32(&base->dir1, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
46 clrsetbits_be32(&base->dir2, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
54 struct gpio_n __iomem *base = data->base; local
59 clrsetbits_be32(&base->dir1, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
61 clrsetbits_be32(&base
74 struct gpio_n __iomem *base = data->base; local
83 struct gpio_n __iomem *base = data->base; local
[all...]
/u-boot/board/armltd/vexpress64/
H A Dpcie.c71 static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, argument
82 base + XR3PCI_ATR_SRC_ADDR_LOW);
83 writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
84 writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
85 writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
86 writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
96 unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0; local
99 xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
102 base += XR3PCI_ATR_TABLE_SIZE;
105 xr3pci_set_atr_entry(base, PHYS_SDRAM_
[all...]
/u-boot/drivers/rtc/
H A Dgoldfish_rtc.c19 * @base: base address for register file
21 void __iomem *base; member in struct:goldfish_rtc
35 void __iomem *base = priv->base; local
40 time_low = ioread32(base + GOLDFISH_TIME_LOW);
41 time_high = ioread32(base + GOLDFISH_TIME_HIGH);
55 void __iomem *base = priv->base; local
62 iowrite32(now >> 32, base
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/u-boot/drivers/clk/at91/
H A Dclk-system.c26 void __iomem *base; member in struct:clk_system
38 static inline bool clk_system_ready(void __iomem *base, int id) argument
42 pmc_read(base, AT91_PMC_SR, &status);
51 pmc_write(sys->base, AT91_PMC_SCER, 1 << sys->id);
56 while (!clk_system_ready(sys->base, sys->id)) {
68 pmc_write(sys->base, AT91_PMC_SCDR, 1 << sys->id);
79 struct clk *at91_clk_register_system(void __iomem *base, const char *name, argument
86 if (!base || !name || !parent_name || id > SYSTEM_MAX_ID)
94 sys->base = base;
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Completed in 154 milliseconds

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