Searched refs:base (Results 276 - 300 of 1028) sorted by relevance

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/u-boot/drivers/crypto/aspeed/
H A Daspeed_acry.c47 phys_addr_t base; member in struct:aspeed_acry
88 writel((u32)ctx, acry->base + ACRY_DMA_DRAM_SADDR);
92 writel(reg, acry->base + ACRY_RSA_PARAM);
95 writel(reg, acry->base + ACRY_DMA_DMEM_TADDR);
98 writel(reg, acry->base + ACRY_CTRL3);
100 writel(ACRY_CTRL1_RSA_DMA | ACRY_CTRL1_RSA_START, acry->base + ACRY_CTRL1);
104 reg = readl(acry->base + ACRY_RSA_INT_STS);
106 writel(reg, acry->base + ACRY_RSA_INT_STS);
113 writel(0x0, acry->base + ACRY_CTRL1);
114 writel(ACRY_CTRL3_SRAM_AHB_ACCESS, acry->base
[all...]
/u-boot/drivers/rng/
H A Drockchip_rng.c75 #define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos))
76 #define trng_read(pdata, pos) readl((pdata)->base + (pos))
84 fdt_addr_t base; member in struct:rk_rng_plat
120 pdata->base + CRYPTO_V1_TRNG_CTRL);
122 rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
125 retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
131 rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
135 rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
150 writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
157 rk_clrsetreg(pdata->base
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/u-boot/drivers/usb/dwc3/
H A Ddwc3-omap.c124 void __iomem *base; member in struct:dwc3_omap
140 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) argument
142 return readl(base + offset);
145 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) argument
147 writel(value, base + offset);
152 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
158 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
165 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
171 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
178 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MIS
[all...]
/u-boot/drivers/spi/
H A Dmtk_spim.c136 * @base: Base address of the spi controller
151 void __iomem *base; member in struct:mtk_spim_priv
168 setbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST);
169 clrbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST);
187 writel(0x0, priv->base + SPI_CFG3_IPM_REG);
188 clrsetbits_le32(priv->base + SPI_CMD_REG,
193 clrsetbits_le32(priv->base + SPI_CFG1_REG,
200 reg_val = readl(priv->base + SPI_CMD_REG);
254 writel(reg_val, priv->base + SPI_CMD_REG);
277 writel(reg_val, priv->base
[all...]
H A Dmtk_snor.c108 void __iomem *base; member in struct:mtk_snor_priv
119 u32 val = readl(priv->base + reg);
123 writel(val, priv->base + reg);
133 writel(cmd, priv->base + MTK_NOR_REG_CMD);
135 ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CMD, reg,
149 writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR(i));
153 writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR3);
217 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(4));
222 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(3));
243 writel(from, priv->base
[all...]
H A Dbcm63xx_spi.c111 void __iomem *base; member in struct:bcm63xx_spi_priv
147 setbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
149 clrbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
173 clrsetbits_8(priv->base + regs[SPI_CLK],
208 writeb_be(0, priv->base + regs[SPI_IR_MASK]);
233 memcpy_toio(priv->base + regs[SPI_TX] + priv->tx_bytes,
270 writew_be(val, priv->base + regs[SPI_CTL]);
272 writeb_be(val, priv->base + regs[SPI_CTL]);
275 writeb_be(SPI_IR_CLEAR_MASK, priv->base + regs[SPI_IR_STAT]);
283 writew_be(cmd, priv->base
[all...]
/u-boot/lib/libavb/
H A Davb_property_descriptor.c124 int base; local
132 base = 10;
134 base = 16;
143 parsed_val *= base;
147 } else if (base == 16 && c >= 'a' && c <= 'f') {
149 } else if (base == 16 && c >= 'A' && c <= 'F') {
/u-boot/drivers/pci/
H A Dpci_msc01.c19 void *base; member in struct:msc01_pci_controller
33 void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
34 void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
44 msc01->base + MSC01_PCI_CFGADDR_OFS);
104 msc01->base = dev_remap_addr(dev);
105 if (!msc01->base)
/u-boot/lib/
H A Dtime.c144 ulong __weak get_timer(ulong base) argument
146 return tick_to_time(get_ticks()) - base;
158 uint64_t __weak get_timer_us(uint64_t base) argument
160 return tick_to_time_us(get_ticks()) - base;
163 unsigned long __weak get_timer_us_long(unsigned long base) argument
165 return timer_get_us() - base;
/u-boot/arch/arm/mach-mvebu/
H A Dcpu.c371 * and sets the correct windows sizes and base addresses accordingly.
379 u64 base = 0; local
389 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
401 base += ((u64)size + 1);
546 static void ahci_mvebu_mbus_config(void __iomem *base) argument
558 writel(0, base + AHCI_WINDOW_CTRL(i));
559 writel(0, base + AHCI_WINDOW_BASE(i));
560 writel(0, base + AHCI_WINDOW_SIZE(i));
568 base
575 ahci_mvebu_regret_option(void __iomem *base) argument
599 xhci_mvebu_mbus_config(void __iomem *base, const struct mbus_dram_target_info *dram) argument
622 board_xhci_enable(fdt_addr_t base) argument
[all...]
H A Ddram.c55 struct sdram_addr_dec *base = local
58 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
63 result = readl(&base->sdram_bank[bank].win_bar);
72 struct sdram_addr_dec *base = local
75 u32 reg = readl(&base->sdram_bank[bank].win_sz);
83 writel(reg, &base->sdram_bank[bank].win_sz);
91 struct sdram_addr_dec *base = local
94 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
98 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
122 u32 reg, base, siz local
[all...]
/u-boot/drivers/net/
H A Daspeed_mdio.c43 void *base; member in struct:aspeed_mdio_priv
62 writel(ctrl, priv->base + ASPEED_MDIO_CTRL);
64 rc = readl_poll_timeout(priv->base + ASPEED_MDIO_DATA, data,
89 writel(ctrl, priv->base + ASPEED_MDIO_CTRL);
91 return readl_poll_timeout(priv->base + ASPEED_MDIO_CTRL, ctrl,
107 priv->base = dev_read_addr_ptr(dev);
/u-boot/drivers/misc/
H A Dnpcm_host_intf.c47 void __iomem *base; local
68 base = dev_read_addr_ptr(dev);
69 if (!base)
81 writel(val, base + ESPIHINDP);
83 val = readl(base + ESPICFG);
86 writel(val, base + ESPICFG);
/u-boot/drivers/mmc/
H A Dmv_sdhci.c25 static void sdhci_mvebu_mbus_config(void __iomem *base) argument
33 writel(0, base + SDHCI_WINDOW_CTRL(i));
34 writel(0, base + SDHCI_WINDOW_BASE(i));
43 base + SDHCI_WINDOW_CTRL(i));
45 /* Write base address to base register */
46 writel(cs->base, base + SDHCI_WINDOW_BASE(i));
H A Dstm32_sdmmc2.c35 fdt_addr_t base; member in struct:stm32_sdmmc2_plat
70 #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
229 writel(ctx->data_length, plat->base + SDMMC_DLEN);
232 writel(data_ctrl, plat->base + SDMMC_DCTRL);
247 writel(idmabase0, plat->base + SDMMC_IDMABASE0);
248 writel(SDMMC_IDMACTRL_IDMAEN, plat->base + SDMMC_IDMACTRL);
258 if (readl(plat->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
259 writel(0, plat->base + SDMMC_CMD);
282 writel(0, plat->base + SDMMC_DCTRL);
289 writel(timeout, plat->base
[all...]
/u-boot/arch/x86/cpu/baytrail/
H A Dcpu.c28 static void hsuart_clock_set(void *base) argument
39 writel(reg, base + BYT_PRV_CLK);
41 writel(reg, base + BYT_PRV_CLK);
51 void *base; local
59 base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
61 hsuart_clock_set(base);
/u-boot/arch/x86/lib/fsp2/
H A Dfsp_support.c28 void *ptr, *base; local
53 /* Initalise the FSP base */
91 base = (void *)fsp->img_base;
92 log_debug("image base %x\n", (uint)base);
99 ret = spi_flash_read_dm(dev, offset, size, base);
103 memcpy(base, (void *)offset, size);
105 ptr = base + (ptr - (void *)buf);
/u-boot/drivers/watchdog/
H A Dmcf_wdt.c61 void __iomem *base; member in struct:mcf_wdt_priv
76 mcf_watchdog_reset(priv->base);
86 mcf_watchdog_init(priv->base, priv->fixed_divider, timeout);
94 struct watchdog_regs *wdog = (struct watchdog_regs *)priv->base;
105 priv->base = dev_read_addr_ptr(dev);
106 if (!priv->base)
/u-boot/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-core.c107 tmp = readl(priv->base + reg);
112 writel(tmp, priv->base + reg);
130 writel(U32_MAX, priv->base + UNIPHIER_PINCTRL_IECTRL);
202 tmp = readl(priv->base + reg);
207 writel(tmp, priv->base + reg);
230 unsigned int base, stride, width, drvctrl, reg, shift; local
240 base = UNIPHIER_PINCTRL_DRVCTRL_BASE;
246 base = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
252 base = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
264 reg = base
[all...]
/u-boot/drivers/phy/
H A Dphy-imx8m-pcie.c62 ulong base; member in struct:imx8_pcie_phy
88 imx8_phy->base + PCIE_PHY_TRSV_REG5);
91 imx8_phy->base + PCIE_PHY_TRSV_REG6);
100 val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
102 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
106 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
113 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
115 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
118 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
120 imx8_phy->base
[all...]
/u-boot/arch/arm/mach-omap2/omap5/
H A Ddra7xx_iodelay.c53 static int calibrate_iodelay(u32 base) argument
58 reg = readl(base + CFG_REG_2_OFFSET);
61 writel(reg, base + CFG_REG_2_OFFSET);
64 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
67 (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
73 static int update_delay_mechanism(u32 base) argument
76 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
79 (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
85 static u32 calculate_delay(u32 base, u16 offset, u16 den) argument
90 refclk_period = readl(base
142 do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, int niodelays) argument
[all...]
/u-boot/drivers/net/mscc_eswitch/
H A Djr2_switch.c355 static void serdes6g_write(void __iomem *base, u32 addr) argument
361 base + HSIO_MCB_SERDES6G_CFG);
364 data = readl(base + HSIO_MCB_SERDES6G_CFG);
368 static void serdes6g_setup(void __iomem *base, uint32_t addr, argument
404 writel(0xfff, base + HSIO_HW_CFGSTAT_HW_CFG);
410 HSIO_ANA_SERDES6G_OB_CFG_POL, base + HSIO_ANA_SERDES6G_OB_CFG);
413 base + HSIO_ANA_SERDES6G_COMMON_CFG);
416 base + HSIO_ANA_SERDES6G_PLL_CFG);
432 base + HSIO_ANA_SERDES6G_IB_CFG);
440 base
581 serdes1g_write(void __iomem *base, u32 addr) argument
594 serdes1g_setup(void __iomem *base, uint32_t addr, phy_interface_t interface) argument
840 get_mdiobus(phys_addr_t base, unsigned long size) argument
[all...]
/u-boot/arch/x86/cpu/quark/
H A Dquark.c26 u32 base, mask; local
52 base = CONFIG_TEXT_BASE & mask;
54 base | MTRR_TYPE_WRBACK);
60 base = CONFIG_ESRAM_BASE & mask;
62 base | MTRR_TYPE_WRBACK);
316 u32 base; local
318 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
319 base &= ~MEM_BAR_EN;
320 rcba = (struct quark_rcba *)base;
367 u32 base, va local
[all...]
/u-boot/drivers/power/regulator/
H A Dpfuze100.c51 #define PFUZE100_FIXED_REG(_name, base, vol) \
58 #define PFUZE100_SW_REG(_name, base, step) \
63 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
65 .stby_reg = (base) + PFUZE100_STBY_OFFSET, \
69 #define PFUZE100_SWB_REG(_name, base, mask, step, voltages) \
74 .vsel_reg = (base), \
79 #define PFUZE100_SNVS_REG(_name, base, mask, voltages) \
83 .vsel_reg = (base), \
88 #define PFUZE100_VGEN_REG(_name, base, step) \
93 .vsel_reg = (base), \
[all...]
/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dmmc.h59 unsigned int base = samsung_get_base_mmc() + local
62 return s5p_sdhci_init(base, index, bus_width);

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