/u-boot/drivers/power/regulator/ |
H A D | stm32-vrefbuf.c | 32 void __iomem *base; member in struct:stm32_vrefbuf 48 if (enable && !(readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR)) { 56 clrbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ); 60 clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR, 71 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, 75 clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR, 87 return readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR; 97 clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, 111 val = readl(priv->base + STM32_VREFBUF_CSR) & STM32_VRS; 129 priv->base [all...] |
/u-boot/include/ |
H A D | vsprintf.h | 18 * @base: The number base to use (0 for the default) 25 * A hex prefix is supported (e.g. 0x123) regardless of the value of @base. 26 * If found, the base is set to hex (16). 28 * If @base is 0: 29 * - an octal '0' prefix (e.g. 0777) sets the base to octal (8). 30 * - otherwise the base defaults to decimal (10). 32 ulong simple_strtoul(const char *cp, char **endp, unsigned int base); 63 * @base: The number base t [all...] |
/u-boot/board/cssi/mcr3000/ |
H A D | mcr3000_gpio.c | 20 void __iomem *base; member in struct:mcr3000_spi_gpio_data 28 clrsetbits_be16(data->base, 7 << 5, (gpio & 7) << 5); 30 clrbits_be16(data->base, 7 << 5); 39 return gpio == ((in_be16(data->base) >> 5) & 7); 73 data->base = map_sysmem(plat->addr, 2);
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/u-boot/drivers/power/acpi_pmc/ |
H A D | sandbox.c | 24 /* Offset of TCO registers from ACPI base I/O address */ 32 ulong base; member in struct:sandbox_pmc_priv 68 ulong base; local 71 base = dm_pci_read_bar32(dev, 0); 72 if (base == FDT_ADDR_T_NONE) 73 return log_msg_ret("No base address", -EINVAL); 74 upriv->pmc_bar0 = map_sysmem(base, 0x2000);
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/u-boot/drivers/reset/ |
H A D | reset-sifive.c | 19 void *base; member in struct:sifive_reset_priv 28 int regval = readl(priv->base + PRCI_RESETREG_OFFSET); 38 writel(regval, priv->base + PRCI_RESETREG_OFFSET); 70 priv->base = dev_remap_addr(dev); 71 if (!priv->base)
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/u-boot/post/lib_powerpc/ |
H A D | load.c | 15 * is 4-byte aligned. The base register points to offset 8. 24 * value of the destination register and the value of the base 172 ulong base = base0; local 183 cpu_post_exec_22w (code, &base, test->offset, &value); 193 cpu_post_exec_21w (code, &base, &value); 199 ret = base == base0 + test->offset ? 0 : -1; 201 ret = base == base0 ? 0 : -1;
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H A D | store.c | 15 * is 4-byte aligned. The base register points to offset 8. 24 * and the value of the base register (it must change for "store 157 ulong base = base0; local 167 cpu_post_exec_12w (code, &base, test->offset, test->value); 177 cpu_post_exec_11w (code, &base, test->value); 183 ret = base == base0 + test->offset ? 0 : -1; 185 ret = base == base0 ? 0 : -1;
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/u-boot/drivers/spi/ |
H A D | spi-sn-f-ospi.c | 110 void __iomem *base; member in struct:f_ospi 128 ospi->base + OSPI_IRQ); 135 val = readl(ospi->base + OSPI_IRQ_STAT_EN); 137 writel(val, ospi->base + OSPI_IRQ_STAT_EN); 144 val = readl(ospi->base + OSPI_IRQ_STAT_EN); 146 writel(val, ospi->base + OSPI_IRQ_STAT_EN); 153 val = readl(ospi->base + OSPI_IRQ_SIG_EN); 155 writel(val, ospi->base + OSPI_IRQ_SIG_EN); 163 val = readl(ospi->base + OSPI_CLK_CTL); 165 writel(val, ospi->base [all...] |
H A D | mtk_snfi_spi.c | 50 void __iomem *base; member in struct:mtk_snfi_priv 100 writel(SF_MAC_EN, priv->base + SNFI_MAC_CTL); 101 writel(outlen, priv->base + SNFI_MAC_OUTL); 102 writel(inlen, priv->base + SNFI_MAC_INL); 104 writel(SF_MAC_EN | SF_TRIG, priv->base + SNFI_MAC_CTL); 106 ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val, 113 ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val, 118 writel(0, priv->base + SNFI_MAC_CTL); 133 setbits_32(priv->base + SNFI_MISC_CTL, SW_RST); 135 ret = readl_poll_timeout(priv->base [all...] |
H A D | spi-qup.c | 177 phys_addr_t base; member in struct:qup_spi_priv 211 while ((readl(priv->base + QUP_OPERATIONAL) & QUP_OP_OUT_FIFO_FULL)) 215 writel(data, priv->base + QUP_OUTPUT_FIFO); 226 while (!(readl(priv->base + QUP_OPERATIONAL) & QUP_DATA_AVAILABLE_FOR_READ)) { 232 return readl(priv->base + QUP_INPUT_FIFO) & 0xff; 248 val = readl(priv->base + reg_addr); 268 clrsetbits_le32(priv->base + QUP_CONFIG, 271 clrsetbits_le32(priv->base + QUP_CONFIG, 276 clrsetbits_le32(priv->base + QUP_CONFIG, 279 clrsetbits_le32(priv->base [all...] |
/u-boot/drivers/watchdog/ |
H A D | starfive_wdt.c | 66 void __iomem *base; member in struct:starfive_wdt_priv 118 writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); 123 writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); 131 val = readl(wdt->base + wdt->variant->control); 133 writel(val, wdt->base + wdt->variant->control); 141 return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value, 156 writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr); 164 writel(val, wdt->base + wdt->variant->load); 172 val = readl(wdt->base + wdt->variant->enable); 174 writel(val, wdt->base [all...] |
/u-boot/drivers/gpio/ |
H A D | dwapb_gpio.c | 37 void __iomem *base; member in struct:gpio_dwapb_plat 44 clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); 53 setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); 56 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 58 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 68 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 70 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 80 gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank)); 94 value = readl(plat->base + GPIO_SWPORT_DR(plat->bank)); 96 value = readl(plat->base 155 fdt_addr_t base; local [all...] |
H A D | rzg2l-gpio.c | 18 setbits_8(data->base + P(port), BIT(pin)); 20 clrbits_8(data->base + P(port), BIT(pin)); 31 pm_state = (readw(data->base + PM(port)) >> (pin * 2)) & PM_MASK; 34 return !!(readb(data->base + PIN(port)) & BIT(pin)); 37 return !!(readb(data->base + P(port)) & BIT(pin)); 58 clrsetbits_le16(data->base + PM(port), PM_MASK << (pin * 2), 100 clrbits_8(data->base + PMC(port), BIT(pin)); 120 pmc_state = readb(data->base + PMC(port)) & BIT(pin); 125 pm_state = (readw(data->base + PM(port)) >> (pin * 2)) & PM_MASK;
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H A D | msm_gpio.c | 28 phys_addr_t base; member in struct:msm_gpio_bank 47 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), 63 writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio)); 79 writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio)); 81 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), 112 return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); 123 if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE) 139 priv->base = dev_read_addr(dev); 142 return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
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/u-boot/drivers/usb/host/ |
H A D | ehci-marvell.c | 61 static void usb_brg_adrdec_setup(struct udevice *dev, void *base) argument 69 writel(0, base + USB_WINDOW_CTRL(i)); 70 writel(0, base + USB_WINDOW_BASE(i)); 81 base + USB_WINDOW_CTRL(0)); 83 /* Write base address to base register */ 84 writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0)); 86 debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n", 87 base + USB_WINDOW_CTRL(0), readl(base 204 u32 size, base, attrib; local [all...] |
/u-boot/arch/arm/mach-uniphier/ |
H A D | dram_init.c | 24 unsigned long base; member in struct:uniphier_dram_map 37 dram_map[0].base = 0x80000000; 66 dram_map[1].base = dram_map[0].base + size; 69 if (dram_map[1].base > sparse_ch1_base) { 72 dram_map[1].base = 0; 76 dram_map[1].base = sparse_ch1_base; 109 dram_map[2].base = dram_map[1].base + size; 238 if (valid_bank_found && prev_top < dram_map[i].base) [all...] |
/u-boot/drivers/net/ |
H A D | higmacv300.c | 110 void __iomem *base; member in struct:higmac_priv 137 writel(val, priv->base + STATION_ADDR_HIGH); 140 writel(val, priv->base + STATION_ADDR_LOW); 150 writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR); 166 fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR)); 167 fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR)); 183 writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR); 186 bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR)); 192 bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR)); 223 bqw_pos = DESC_CNT(readl(priv->base [all...] |
/u-boot/drivers/mmc/ |
H A D | arm_pl180_mmci.c | 49 hoststatus = readl(&host->base->status) & statusmask; 52 writel(statusmask, &host->base->status_clear); 63 cmd->response[0] = readl(&host->base->response0); 64 cmd->response[1] = readl(&host->base->response1); 65 cmd->response[2] = readl(&host->base->response2); 66 cmd->response[3] = readl(&host->base->response3); 91 writel((u32)cmd->cmdarg, &host->base->argument); 93 writel(sdi_cmd, &host->base->command); 102 u32 sdi_pwr = readl(&host->base->power) & ~SDI_PWR_OPD; 103 writel(sdi_pwr, &host->base [all...] |
/u-boot/drivers/i2c/ |
H A D | qup_i2c.c | 141 phys_addr_t base; member in struct:qup_i2c_priv 166 state = readl(qup->base + QUP_STATE); 198 writel(state, qup->base + QUP_STATE); 217 val = readl(qup->base + reg_addr); 241 writel(qup->config_run | write_cnt, qup->base + QUP_MX_WRITE_CNT); 244 writel(qup->config_run | read_cnt, qup->base + QUP_MX_READ_CNT); 248 writel(qup_config, qup->base + QUP_CONFIG); 253 return readl(qup->base + QUP_IN_FIFO_BASE); 258 writel(word, qup->base + QUP_OUT_FIFO_BASE); 289 writel(QUP_OUT_SVC_FLAG, qup->base [all...] |
/u-boot/drivers/pinctrl/renesas/ |
H A D | pinctrl-rza1.c | 36 void __iomem *base; member in struct:r7s72100_pfc_plat 44 clrsetbits_le16(plat->base + PFCAE(bank), BIT(line), 46 clrsetbits_le16(plat->base + PFCE(bank), BIT(line), 48 clrsetbits_le16(plat->base + PFC(bank), BIT(line), 51 clrsetbits_le16(plat->base + PIBC(bank), BIT(line), 53 clrsetbits_le16(plat->base + PBDC(bank), BIT(line), 56 setbits_le32(plat->base + PMCSR(bank), BIT(line + 16) | BIT(line)); 58 setbits_le16(plat->base + PIPC(bank), BIT(line)); 119 plat->base = (void __iomem *)addr_base;
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/u-boot/drivers/rng/ |
H A D | iproc_rng200.c | 36 void __iomem *base; member in struct:iproc_rng200_plat 41 void __iomem *rng_base = pdata->base; 56 void __iomem *rng_base = pdata->base; 97 status = readl(priv->base + RNG_INT_STATUS_OFFSET); 109 if ((readl(priv->base + RNG_FIFO_COUNT_OFFSET) & 114 *(u32 *)buf = readl(priv->base + 120 u32 rnd_number = readl(priv->base + 158 pdata->base = devfdt_map_physmem(dev, sizeof(void *)); 159 if (!pdata->base)
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/u-boot/drivers/button/ |
H A D | button-qcom-pmic.c | 30 u32 base; member in struct:qcom_pmic_btn_priv 46 int reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS); 108 u64 base; local 128 base = dev_read_addr(dev->parent); 129 if (base == FDT_ADDR_T_NONE) { 134 priv->base = base; 137 ret = pmic_reg_read(priv->pmic, priv->base + REG_TYPE); 143 ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE);
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/u-boot/drivers/pinctrl/exynos/ |
H A D | pinctrl-exynos.c | 32 * base: base address of the pin controller. 35 unsigned int num_conf, unsigned long base) 40 val = readl(base + conf[idx].offset); 43 writel(val, base + conf[idx].offset); 149 reg = priv->base + bank->offset; 166 fdt_addr_t base; local 172 base = dev_read_addr(dev); 173 if (base == FDT_ADDR_T_NONE) 176 priv->base 34 exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf, unsigned int num_conf, unsigned long base) argument [all...] |
/u-boot/arch/x86/lib/ |
H A D | pinctrl_ich6.c | 33 static int ich6_pinctrl_set_value(uint16_t base, unsigned offset, int value) argument 36 setio_32(base, 1UL << offset); 38 clrio_32(base, 1UL << offset); 43 static int ich6_pinctrl_set_function(uint16_t base, unsigned offset, int func) argument 46 setio_32(base, 1UL << offset); 48 clrio_32(base, 1UL << offset); 53 static int ich6_pinctrl_set_direction(uint16_t base, unsigned offset, int dir) argument 56 setio_32(base, 1UL << offset); 58 clrio_32(base, 1UL << offset); 168 * Get the memory/io base addres [all...] |
/u-boot/arch/x86/cpu/ivybridge/ |
H A D | bd82x6x.c | 164 /* make sure the LPC is inited since it provides the gpio base */ 183 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ 197 u32 base; local 205 * GPIO base address register bit0 is reserved (read returns 0), 209 dm_pci_read_config32(dev, GPIO_BASE, &base); 210 if (base == 0x00000000 || base == 0xffffffff) { 221 *gbasep = base & 1 ? base & ~3 : base [all...] |