Searched refs:base (Results 201 - 225 of 1028) sorted by relevance

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/u-boot/drivers/mtd/nand/raw/brcmnand/
H A Dbcm6753_nand.c17 void __iomem *base; member in struct:bcm6753_nand_soc
43 void __iomem *mmio = priv->base + BCM6753_NAND_INT;
61 void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN;
84 dev_read_resource_byname(pdev, "nand-int-base", &res);
85 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
86 if (IS_ERR(priv->base))
87 return PTR_ERR(priv->base);
93 brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN);
94 brcmnand_writel(0, priv->base + BCM6753_NAND_INT);
H A Dbcm63158_nand.c19 void __iomem *base; member in struct:bcm63158_nand_soc
45 void __iomem *mmio = priv->base + BCM63158_NAND_INT;
63 void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN;
86 dev_read_resource_byname(pdev, "nand-int-base", &res);
87 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
88 if (IS_ERR(priv->base))
89 return PTR_ERR(priv->base);
95 brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN);
96 brcmnand_writel(0, priv->base + BCM63158_NAND_INT);
/u-boot/drivers/spi/
H A Dnpcm_pspi.c33 void __iomem *base; member in struct:npcm_pspi_priv
59 val = readw(priv->base + PSPI_CTL1);
61 writew(val, priv->base + PSPI_CTL1);
68 val = readw(priv->base + PSPI_CTL1);
70 writew(val, priv->base + PSPI_CTL1);
78 void __iomem *base = priv->base; local
93 ret = readb_poll_timeout(base + PSPI_STAT, val,
100 writeb(*tx++, base + PSPI_DATA);
102 writeb(0, base
[all...]
H A Dti_qspi.c69 #define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
104 struct ti_qspi_regs *base; member in struct:ti_qspi_priv
129 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
130 &priv->base->clk_ctrl);
132 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
139 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
141 readl(&priv->base->cmd);
204 writel(data, &priv->base->data3);
206 writel(data, &priv->base->data2);
208 writel(data, &priv->base
[all...]
H A Docteon_spi.c77 void __iomem *base; /* Register base address */ member in struct:octeon_spi
124 void *base = priv->base; local
128 mpi_sts = readq(base + MPI_STS);
146 void *base = priv->base; local
156 mpi_cfg = readq(base + MPI_CFG);
159 writeq(mpi_cfg, base + MPI_CFG);
160 mpi_cfg = readq(base
177 void *base = priv->base; local
201 void *base = priv->base; local
293 void *base = priv->base; local
[all...]
/u-boot/drivers/misc/imx_ele/
H A Dele_mu.c20 struct mu_type *base; member in struct:imx8ulp_mu
28 void mu_hal_init(ulong base) argument
30 struct mu_type *mu_base = (struct mu_type *)base;
36 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg) argument
38 struct mu_type *mu_base = (struct mu_type *)base;
61 int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) argument
63 struct mu_type *mu_base = (struct mu_type *)base;
96 static int imx8ulp_mu_read(struct mu_type *base, void *data) argument
106 ret = mu_hal_receivemsg((ulong)base, 0, (u32 *)msg);
119 ret = mu_hal_receivemsg((ulong)base, coun
129 imx8ulp_mu_write(struct mu_type *base, void *data) argument
[all...]
/u-boot/drivers/serial/
H A Dserial_lpuart.c155 struct lpuart_fsl *base = plat->reg; local
171 __raw_writeb(sbr >> 8, &base->ubdh);
172 __raw_writeb(sbr & 0xff, &base->ubdl);
177 struct lpuart_fsl *base = plat->reg; local
178 if (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
183 return __raw_readb(&base->ud);
189 struct lpuart_fsl *base = plat->reg; local
191 if (!(__raw_readb(&base->us1) & US1_TDRE))
194 __raw_writeb(c, &base->ud);
201 struct lpuart_fsl *base local
216 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg; local
245 struct lpuart_fsl_reg32 *base = plat->reg; local
314 struct lpuart_fsl_reg32 *base = plat->reg; local
335 struct lpuart_fsl_reg32 *base = plat->reg; local
356 struct lpuart_fsl_reg32 *base = plat->reg; local
370 struct lpuart_fsl_reg32 *base = plat->reg; local
388 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; local
[all...]
H A Dserial_cortina.c62 void __iomem *base; member in struct:ca_uart_priv
72 uart_ctrl = readl(priv->base + UCFG);
75 writel(uart_ctrl, priv->base + UCFG);
79 writel(sample, priv->base + URX_SAMPLE);
89 ch = readl(priv->base + URX_DATA) & 0xFF;
100 status = readl(priv->base + UINFO);
104 writel(ch, priv->base + UTX_DATA);
114 status = readl(priv->base + UINFO);
129 writel(uart_ctrl, priv->base + UCFG);
138 priv->base
[all...]
/u-boot/drivers/i2c/
H A Drz_riic.c144 void __iomem *base; member in struct:riic_priv
157 ret = wait_for_bit_8(priv->base + RIIC_ICCR2, ICCR2_BBSY, 0,
174 while (!((icsr2 = readb(priv->base + RIIC_ICSR2)) & bit)) {
179 bit, icsr2, readb(priv->base + RIIC_ICCR2));
193 if (readb(priv->base + RIIC_ICSR2) & ICSR2_NACKF) {
196 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_NACKF);
197 setbits_8(priv->base + RIIC_ICCR2, ICCR2_SP);
198 readb(priv->base + RIIC_ICDRR); /* dummy read */
219 writeb(buf[i], priv->base + RIIC_ICDRT);
231 setbits_8(priv->base
[all...]
H A Dmxc_i2c.c156 ulong base = i2c_bus->base; local
162 if (!base)
166 writeb(idx, base + (IFDR << reg_shift));
169 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
170 writeb(0, base + (I2SR << reg_shift));
184 ulong base = i2c_bus->base; local
187 sr = readb(base + (I2SR << reg_shift));
190 writeb(sr | I2SR_IAL, base
217 ulong base = i2c_bus->base; local
247 ulong base = i2c_bus->base; local
267 ulong base = i2c_bus->base; local
469 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base; local
552 ulong base = i2c_bus->base; local
653 ulong base = i2c_bus->base; local
[all...]
/u-boot/drivers/clk/imx/
H A Dclk-pll14xx.c48 void __iomem *base; member in struct:clk_pll14xx
136 pll_div = readl(pll->base + 4);
154 pll_div_ctl0 = readl(pll->base + 4);
155 pll_div_ctl1 = readl(pll->base + 8);
211 return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
229 tmp = readl(pll->base + 4);
234 writel(tmp, pll->base + 4);
240 tmp = readl(pll->base);
242 writel(tmp, pll->base);
246 writel(tmp, pll->base);
391 imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk) argument
[all...]
/u-boot/arch/arm/mach-omap2/
H A Demif-common.c28 void set_lpmode_selfrefresh(u32 base) argument
30 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
50 inline u32 emif_num(u32 base) argument
52 if (base == EMIF1_BASE)
54 else if (base == EMIF2_BASE)
60 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) argument
63 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
71 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
81 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) argument
83 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
90 emif_reset_phy(u32 base) argument
100 do_lpddr2_init(u32 base, u32 cs) argument
131 lpddr2_init(u32 base, const struct emif_regs *regs) argument
165 do_ext_phy_settings(u32 base, const struct emif_regs *regs) argument
169 emif_update_timings(u32 base, const struct emif_regs *regs) argument
206 omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) argument
257 update_hwleveling_output(u32 base, const struct emif_regs *regs) argument
301 dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) argument
340 dra7_reset_ddr_data(u32 base, u32 size) argument
353 dra7_enable_ecc(u32 base, const struct emif_regs *regs) argument
416 dra7_ddr3_init(u32 base, const struct emif_regs *regs) argument
477 omap5_ddr3_init(u32 base, const struct emif_regs *regs) argument
506 ddr3_init(u32 base, const struct emif_regs *regs) argument
877 get_emif_mem_size(u32 base) argument
1116 is_lpddr2_sdram_present(u32 base, u32 cs, struct lpddr2_device_details *lpddr2_device) argument
1207 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; local
1229 do_sdram_init(u32 base) argument
1315 emif_post_init_config(u32 base) argument
1329 dmm_init(u32 base) argument
1471 do_bug0039_workaround(u32 base) argument
[all...]
/u-boot/drivers/clk/at91/
H A Dclk-sam9x60-usb.c20 void __iomem *base; member in struct:sam9x60_usb
48 pmc_read(usb->base, usb->layout->offset, &val);
51 pmc_write(usb->base, usb->layout->offset, val);
65 pmc_read(usb->base, usb->layout->offset, &val);
84 pmc_read(usb->base, usb->layout->offset, &val);
87 pmc_write(usb->base, usb->layout->offset, val);
99 sam9x60_clk_register_usb(void __iomem *base, const char *name, argument
109 if (!base || !name || !parent_names || !num_parents ||
118 usb->base = base;
[all...]
H A Dclk-generic.c25 void __iomem *base; member in struct:clk_gck
41 pmc_write(gck->base, gck->layout->offset,
43 pmc_update_bits(gck->base, gck->layout->offset,
54 pmc_write(gck->base, gck->layout->offset,
56 pmc_update_bits(gck->base, gck->layout->offset,
78 pmc_write(gck->base, gck->layout->offset,
80 pmc_update_bits(gck->base, gck->layout->offset,
104 pmc_write(gck->base, gck->layout->offset,
106 pmc_update_bits(gck->base, gck->layout->offset,
123 pmc_write(gck->base, gc
142 at91_clk_register_generic(void __iomem *base, const struct clk_pcr_layout *layout, const char *name, const char * const *parent_names, const u32 *clk_mux_table, const u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range) argument
[all...]
H A Dclk-master.c44 void __iomem *base; member in struct:clk_master
61 pmc_read(master->base, AT91_PMC_SR, &status);
91 pmc_read(master->base, master->layout->offset, &mckr);
109 struct clk *at91_clk_register_master_pres(void __iomem *base, argument
120 if (!base || !name || !num_parents || !parent_names ||
130 master->base = base;
134 pmc_read(master->base, master->layout->offset, &val);
167 pmc_read(master->base, master->layout->offset, &mckr);
185 struct clk *at91_clk_register_master_div(void __iomem *base, argument
332 at91_clk_sama7g5_register_master(void __iomem *base, const char *name, const char * const *parent_names, int num_parents, const u32 *mux_table, const u32 *clk_mux_table, bool critical, u8 id) argument
[all...]
/u-boot/drivers/pci/
H A Dpcie_ecam_synquacer.c119 static void or_writel(void *base, u32 offs, u32 val) argument
121 writel(readl(base + offs) | val, base + offs);
124 static void masked_writel(void *base, u32 offs, u32 mask, u32 val) argument
133 data = (readl(base + offs) & ~mask) | val;
137 writel(data, base + offs);
140 static u32 masked_readl(void *base, u32 offs, u32 mask) argument
145 data = readl(base + offs);
200 * @cfg_base: The base address of memory mapped configuration space
337 /* Find the correct pair of the DBI/EXS base addres
374 void *base = pcie->exs_base; local
456 void *base = pcie->exs_base; local
[all...]
/u-boot/drivers/net/
H A Dliteeth.c35 void __iomem *base; member in struct:liteeth
55 if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {
60 rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);
61 len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);
74 litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
84 litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
85 litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1);
88 litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 1);
89 litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 1);
98 litex_write8(priv->base
[all...]
/u-boot/lib/
H A Dsscanf.c45 * @base: number's base
56 str_to_int_convert(const char **nptr, int base, unsigned int unsign) argument
68 * If base is 0, allow 0x for hex and 0 for octal, else
69 * assume decimal; if base is already 16, allow 0x.
86 if ((base == 0 || base == 16) &&
90 base = 16;
92 if (base == 0)
93 base
162 strtoq(const char *nptr, char **endptr, int base) argument
197 strtouq(const char *nptr, char **endptr, int base) argument
375 int base; /* base argument to strtoq/strtouq */ local
[all...]
/u-boot/drivers/usb/host/
H A Ddwc3-octeon-glue.c72 static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base) argument
79 int index = ((u64)base >> 24) & 1;
125 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
131 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
137 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
140 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
147 static int dwc3_octeon_clocks_start(struct udevice *dev, void __iomem *base) argument
156 void __iomem *uctl_ctl_reg = base;
302 if (dwc3_octeon_config_power(dev, base)) {
328 static void dwc3_octeon_set_endian_mode(void __iomem *base) argument
340 dwc3_octeon_phy_reset(void __iomem *base) argument
351 void __iomem *base; local
[all...]
/u-boot/drivers/rtc/
H A Dstm32_rtc.c64 fdt_addr_t base; member in struct:stm32_rtc_priv
72 tr = readl(priv->base + STM32_RTC_TR);
73 dr = readl(priv->base + STM32_RTC_DR);
98 writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
99 writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
106 writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
112 u32 isr = readl(priv->base + STM32_RTC_ISR);
116 writel(isr, priv->base + STM32_RTC_ISR);
118 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
130 u32 isr = readl(priv->base
[all...]
/u-boot/drivers/net/pfe_eth/
H A Dpfe_hw.c620 * @param[in] base BMU block base address
622 static inline void bmu_reset(void *base) argument
624 writel(CORE_SW_RESET, base + BMU_CTRL);
627 while (readl(base + BMU_CTRL) & CORE_SW_RESET)
633 * @param[in] base BMU block base address
635 void bmu_enable(void *base) argument
637 writel(CORE_ENABLE, base + BMU_CTRL);
642 * @param[in] base BM
644 bmu_disable(void *base) argument
654 bmu_set_config(void *base, struct bmu_cfg *cfg) argument
669 bmu_init(void *base, struct bmu_cfg *cfg) argument
683 gpi_reset(void *base) argument
692 gpi_enable(void *base) argument
701 gpi_disable(void *base) argument
711 gpi_set_config(void *base, struct gpi_cfg *cfg) argument
743 gpi_init(void *base, struct gpi_cfg *cfg) argument
[all...]
/u-boot/drivers/mmc/
H A Dmxcmmc.c105 struct mxcmci_regs *base; member in struct:mxcmci_host
140 writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
142 &host->base->str_stp_clk);
145 writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
147 writel(0xff, &host->base->res_to);
158 writel(nob, &host->base->nob);
159 writel(blksz, &host->base->blk_len);
189 writel(cmd->cmdidx, &host->base->cmd);
190 writel(cmd->cmdarg, &host->base->arg);
191 writel(cmdat, &host->base
[all...]
/u-boot/arch/mips/mach-octeon/
H A Dcvmx-global-resources.c128 * @param base 64bit physical address of the complete structure
135 static inline u64 __cvmx_struct_get_unsigned_field(u64 base, int offset, argument
138 base = (1ull << 63) | (base + offset);
141 return cvmx_read64_uint32(base);
143 return cvmx_read64_uint64(base);
154 * @param base 64bit physical address of the complete structure
160 static inline void __cvmx_struct_set_unsigned_field(u64 base, int offset, argument
163 base = (1ull << 63) | (base
239 u64 base = 0; local
412 int base; local
446 cvmx_reserve_global_resource_range(struct global_resource_tag tag, u64 owner, int base, int nelements) argument
458 cvmx_free_global_resource_range_with_base(struct global_resource_tag tag, int base, int nelements) argument
[all...]
/u-boot/drivers/bus/
H A Duniphier-system-bus.c11 #define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
74 fdt_addr_t base; local
77 base = dev_read_addr(dev);
78 if (base == FDT_ADDR_T_NONE)
81 membase = devm_ioremap(dev, base, SZ_1K);
/u-boot/arch/arm/include/asm/arch-vf610/
H A Dgpio.h25 u32 base; member in struct:vybrid_gpio_plat

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