/u-boot/arch/arm/mach-mvebu/armada3700/ |
H A D | cpu.c | 77 static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size) argument 91 if (base) { 93 *base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY; 137 u32 base, tgt, size; local 141 if (get_cpu_dec_win(win, &tgt, &base, &size)) 152 mvebu_mem_map[region].phys = base; 153 mvebu_mem_map[region].virt = base; 178 u32 base, tgt, size; local 181 if (get_cpu_dec_win(win, &tgt, &base, &size)) 194 gd->ram_size += get_ram_size((void *)(size_t)base, siz 201 size_t base, size; member in struct:a3700_dram_window 228 u32 base, tgt, size; local 292 u32 base, tgt; local 319 u32 base, lowest_cpu_addr, fix_offset; local [all...] |
/u-boot/drivers/net/fm/ |
H A D | tgec.c | 31 struct tgec *regs = mac->base; 58 struct tgec *regs = mac->base; 65 struct tgec *regs = mac->base; 72 struct tgec *regs = mac->base; 94 void init_tgec(struct fsl_enet_mac *mac, void *base, argument 97 mac->base = base;
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H A D | memac.c | 21 struct memac *regs = mac->base; 38 struct memac *regs = mac->base; 46 struct memac *regs = mac->base; 53 struct memac *regs = mac->base; 73 struct memac *regs = mac->base; 139 void init_memac(struct fsl_enet_mac *mac, void *base, argument 142 debug("%s: @ %p, mdio @ %p\n", __func__, base, phyregs); 143 mac->base = base;
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/u-boot/drivers/timer/ |
H A D | npcm-timer.c | 40 void __iomem *base; member in struct:npcm_timer_priv 51 val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK; 69 priv->base = dev_read_addr_ptr(dev); 70 if (!priv->base) 89 writel(0, priv->base + TCR0); 90 writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0); 92 priv->base + TCR0);
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/u-boot/drivers/reset/ |
H A D | reset-hisilicon.c | 16 void __iomem *base; member in struct:hisi_reset_priv 24 val = readl(priv->base + rst->data); 29 writel(val, priv->base + rst->data); 39 val = readl(priv->base + rst->data); 44 writel(val, priv->base + rst->data); 91 priv->base = dev_remap_addr(dev); 92 if (!priv->base)
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H A D | reset-mtmips.c | 18 void __iomem *base; member in struct:mtmips_reset_priv 25 setbits_32(priv->base, BIT(reset_ctl->id)); 34 clrbits_32(priv->base, BIT(reset_ctl->id)); 53 priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); 54 if (!priv->base)
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/u-boot/drivers/hwspinlock/ |
H A D | stm32_hwspinlock.c | 21 fdt_addr_t base; member in struct:stm32mp1_hws_priv 32 status = readl(priv->base + index * sizeof(u32)); 37 priv->base + index * sizeof(u32)); 39 status = readl(priv->base + index * sizeof(u32)); 53 writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32)); 64 priv->base = dev_read_addr(dev); 65 if (priv->base == FDT_ADDR_T_NONE)
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/u-boot/drivers/clk/qcom/ |
H A D | clock-qcom.c | 51 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) argument 53 if (readl(base + gpll0->status) & gpll0->status_bit) 56 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); 58 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) 66 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) argument 70 setbits_le32(base + vclk->ena_vote, vclk->vote_bit); 72 val = readl(base + vclk->cbcr_reg); 107 void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, argument 123 writel(m_val & mask, base + cmd_rcgr + RCG_M_REG); 124 writel(n_val & mask, base 146 clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source) argument 293 void __iomem *base = dev_get_priv(rst->dev); local 344 void __iomem *base = dev_get_priv(pwr->dev); local [all...] |
/u-boot/drivers/clk/mediatek/ |
H A D | clk-mtk.c | 57 static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, argument 68 writel(val, base + mux->mux_clr_reg); 71 writel(val, base + mux->mux_set_reg); 74 writel(BIT(mux->upd_shift), base + mux->upd_reg); 77 val = readl(base + mux->mux_reg); 81 writel(val, base + mux->mux_reg); 128 val = readl(priv->base + pll->pd_reg); 134 writel(val, priv->base + pll->pd_reg); 135 val = readl(priv->base + pll->pcw_reg); 143 chg = readl(priv->base [all...] |
/u-boot/drivers/net/ |
H A D | mt7628-eth.c | 136 void __iomem *base; /* frame engine base address */ member in struct:mt7628_eth_dev 137 void __iomem *eth_sw_base; /* switch base address */ 162 void __iomem *base = priv->eth_sw_base; local 165 ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set, 178 void __iomem *base = priv->eth_sw_base; local 191 base + MT7628_SWITCH_PCR0); 198 status = readl(base + MT7628_SWITCH_PCR1); 207 void __iomem *base = priv->eth_sw_base; local 220 writel(data, base 287 void __iomem *base = priv->eth_sw_base; local 341 void __iomem *base = priv->base; local 348 void __iomem *base = priv->base; local 364 void __iomem *base = priv->base; local 385 void __iomem *base = priv->base; local 462 void __iomem *base = priv->base; local 481 void __iomem *base = priv->base; local [all...] |
/u-boot/drivers/spi/ |
H A D | apple_spi.c | 110 void *base; member in struct:apple_spi_priv 116 writel(on ? 0 : APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN); 127 fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT); 132 writel(data, priv->base + APPLE_SPI_TXDATA); 148 fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT); 151 data = readl(priv->base + APPLE_SPI_RXDATA); 179 priv->base + APPLE_SPI_CTRL); 182 writel(txlen, priv->base + APPLE_SPI_TXCNT); 183 writel(rxlen, priv->base + APPLE_SPI_RXCNT); 189 writel(APPLE_SPI_CTRL_RUN, priv->base [all...] |
H A D | mt7621_spi.c | 56 void __iomem *base; member in struct:mt7621_spi 65 setbits_le32(rs->base + MT7621_SPI_MASTER, 67 iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR); 69 iowrite32(0, rs->base + MT7621_SPI_POLAR); 72 rs->base + MT7621_SPI_TRANS); 73 clrbits_le32(rs->base + MT7621_SPI_MASTER, 84 reg = ioread32(rs->base + MT7621_SPI_MASTER); 104 iowrite32(reg, rs->base + MT7621_SPI_MASTER); 125 reg = ioread32(rs->base + MT7621_SPI_MASTER); 128 iowrite32(reg, rs->base [all...] |
/u-boot/drivers/pinctrl/nexell/ |
H A D | pinctrl-s5pxx18.c | 42 static int nx_gpio_open_module(void *base) argument 44 writel(0xFFFFFFFF, base + GPIOX_SLEW_DISABLE_DEFAULT); 45 writel(0xFFFFFFFF, base + GPIOX_DRV1_DISABLE_DEFAULT); 46 writel(0xFFFFFFFF, base + GPIOX_DRV0_DISABLE_DEFAULT); 47 writel(0xFFFFFFFF, base + GPIOX_PULLSEL_DISABLE_DEFAULT); 48 writel(0xFFFFFFFF, base + GPIOX_PULLENB_DISABLE_DEFAULT); 52 static void nx_gpio_set_pad_function(void *base, u32 pin, u32 padfunc) argument 56 nx_gpio_set_bit2(base + reg, pin % 16, padfunc); 59 static void nx_gpio_set_drive_strength(void *base, u32 pin, u32 drv) argument 61 nx_gpio_set_bit(base 65 nx_gpio_set_pull_mode(void *base, u32 pin, u32 mode) argument 77 nx_alive_set_pullup(void *base, u32 pin, bool enable) argument [all...] |
/u-boot/drivers/i2c/ |
H A D | rcar_iic.c | 21 void __iomem *base; member in struct:rcar_iic_priv 54 if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) 67 icsr = readb(priv->base + RCAR_IIC_ICSR); 83 if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR))) 93 clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); 94 setbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); 96 writeb(priv->iccl, priv->base + RCAR_IIC_ICCL); 97 writeb(priv->icch, priv->base + RCAR_IIC_ICCH); 98 writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC); 101 priv->base [all...] |
H A D | i2c-microchip.c | 79 * @base: pointer to register struct 89 void __iomem *base; member in struct:mpfs_i2c_bus 106 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL); 109 writel(ctrl, bus->base + MPFS_I2C_CTRL); 114 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL); 117 writel(ctrl, bus->base + MPFS_I2C_CTRL); 122 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL); 125 writel(ctrl, bus->base + MPFS_I2C_CTRL); 136 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL); 139 writel(ctrl, bus->base [all...] |
H A D | geni_i2c.c | 78 phys_addr_t base; member in struct:geni_i2c_priv 124 writel(m_cmd, geni->base + SE_GENI_M_CMD0); 132 writel(0, geni->base + SE_GENI_CLK_SEL); 135 writel(val, geni->base + GENI_SER_M_CLK_CFG); 140 writel(val, geni->base + SE_I2C_SCL_COUNTERS); 142 writel(0xffffffff, geni->base + SE_GENI_M_IRQ_CLEAR); 152 u32 status = readl(geni->base + SE_GENI_M_IRQ_STATUS); 161 writel(status, geni->base + SE_GENI_M_IRQ_CLEAR); 162 writel(0, geni->base + SE_GENI_TX_WATERMARK_REG); 181 writel(tx, geni->base [all...] |
/u-boot/drivers/crypto/fsl/ |
H A D | dcp_rng.c | 51 unsigned long base; member in struct:imx_rngc_priv 62 status = readl(priv->base + RNGC_STATUS); 73 *(u32 *)buffer = readl(priv->base + RNGC_FIFO); 91 cmd = readl(priv->base + RNGC_COMMAND); 92 writel(cmd | RNGC_CMD_CLR_ERR, priv->base + RNGC_COMMAND); 97 cmd = readl(priv->base + RNGC_COMMAND); 98 writel(cmd | RNGC_CMD_SEED, priv->base + RNGC_COMMAND); 103 status = readl(priv->base + RNGC_STATUS); 104 err_reg = readl(priv->base + RNGC_ERROR); 122 ctrl = readl(priv->base [all...] |
/u-boot/drivers/clk/at91/ |
H A D | clk-utmi.c | 33 void __iomem *base; member in struct:clk_utmi 92 pmc_update_bits(utmi->base, AT91_CKGR_UCKR, uckr, uckr); 94 while (!clk_utmi_ready(utmi->base)) { 106 pmc_update_bits(utmi->base, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0); 123 struct clk *at91_clk_register_utmi(void __iomem *base, struct udevice *dev, argument 131 if (!base || !dev || !name || !parent_name) 143 utmi->base = base; 192 pmc_write(utmi->base, AT91_PMC_XTALF, val); 202 struct clk *at91_clk_sama7g5_register_utmi(void __iomem *base, argument [all...] |
/u-boot/include/linux/ |
H A D | bitfield.h | 25 * from which they extract the base mask and shift amount. 124 #define ____MAKE_OP(type, base, to, from) \ 125 static __always_inline __##type type##_encode_bits(base v, base field) \ 132 base val, base field) \ 137 base val, base field) \ 141 static __always_inline base type##_get_bits(__##type v, base fiel [all...] |
/u-boot/drivers/net/qe/ |
H A D | dm_qe_uec_phy.c | 22 struct ucc_mii_mng *base; member in struct:qe_uec_mdio_priv 29 struct ucc_mii_mng *regs = priv->base; 64 struct ucc_mii_mng *regs = priv->base; 95 fdt_size_t base; local 100 priv->base = dev_read_addr_ptr(dev); 101 base = (fdt_size_t)priv->base; 129 /* check if priv->base in start end */ 130 if (base > addr && base < (add [all...] |
/u-boot/drivers/watchdog/ |
H A D | mpc8xxx_wdt.c | 29 struct mpc8xxx_wdt __iomem *base; member in struct:mpc8xxx_wdt_priv 36 out_be16(&priv->base->swsrr, 0x556c); /* write magic1 */ 37 out_be16(&priv->base->swsrr, 0xaa39); /* write magic2 */ 62 out_be32(&priv->base->swcrr, val); 64 if (!(in_be32(&priv->base->swcrr) & SWCRR_SWEN)) 74 clrbits_be32(&priv->base->swcrr, SWCRR_SWEN); 76 if (in_be32(&priv->base->swcrr) & SWCRR_SWEN) 85 priv->base = (void __iomem *)devfdt_remap_addr(dev); 87 if (!priv->base)
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H A D | stm32mp_wdt.c | 42 fdt_addr_t base; /* registers addr in physical memory */ member in struct:stm32mp_wdt_priv 50 writel(KR_KEY_RELOAD, priv->base + IWDG_KR); 72 writel(KR_KEY_EWA, priv->base + IWDG_KR); 73 writel(PR_256, priv->base + IWDG_PR); 74 writel(reload - 1, priv->base + IWDG_RLR); 77 writel(KR_KEY_ENABLE, priv->base + IWDG_KR); 80 ret = readl_poll_timeout(priv->base + IWDG_SR, val, 99 priv->base = dev_read_addr(dev); 100 if (priv->base == FDT_ADDR_T_NONE)
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/u-boot/include/ |
H A D | exports.h | 44 unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); 45 int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); 48 long simple_strtol(const char *cp, char **endp, unsigned int base); 50 unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); 51 unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
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/u-boot/arch/mips/mach-octeon/ |
H A D | cvmx-range.c | 31 #define addr_of_element(base, index) \ 32 (1ull << 63 | ((base) + sizeof(u64) + (index) * sizeof(u64))) 33 #define addr_of_size(base) (1ull << 63 | (base)) 164 int cvmx_range_reserve(u64 range_addr, u64 owner, u64 base, argument 168 u64 up = base + cnt; 172 debug("ERROR: %s: invalid base or cnt. range_addr=0x%llx, owner=0x%llx, size=%d base+cnt=%d\n", 178 for (i = base; i < up; i++) { 185 debug("%s: resource already reserved base 208 u64 base = bases[i]; local 235 u64 base = bases[i]; local 243 cvmx_range_free_with_base(u64 range_addr, int base, int cnt) argument [all...] |
/u-boot/drivers/core/ |
H A D | simple-bus.c | 20 if (addr >= plat->base && addr < plat->base + plat->size) 21 addr = (addr - plat->base) + plat->target; 41 plat->base = caddr; 51 plat->base = cell[0];
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