Searched hist:70 (Results 1 - 25 of 27) sorted by relevance
| /freebsd-10-stable/usr.sbin/mtree/ | ||
| H A D | Makefile | diff 262648 Sat Mar 01 01:48:01 MST 2014 brooks MFC: 261298 Merge from CheriBSD: commit 70b8f0c127db6b80411789d237b403cc64a93573 Author: Brooks Davis <brooks@one-eyed-alien.net> Date: Mon Jan 27 22:53:57 2014 +0000 Move mtree.5 to usr.sbin/nmtree. Remove note that mtree 2.0 format files aren't supported. Sponsored by: DARPA, AFRL 262648 Sat Mar 01 01:48:01 MST 2014 brooks MFC: 261298 Merge from CheriBSD: commit 70b8f0c127db6b80411789d237b403cc64a93573 Author: Brooks Davis <brooks@one-eyed-alien.net> Date: Mon Jan 27 22:53:57 2014 +0000 Move mtree.5 to usr.sbin/nmtree. Remove note that mtree 2.0 format files aren't supported. Sponsored by: DARPA, AFRL |
| H A D | mtree.5 | diff 262648 Sat Mar 01 01:48:01 MST 2014 brooks MFC: 261298 Merge from CheriBSD: commit 70b8f0c127db6b80411789d237b403cc64a93573 Author: Brooks Davis <brooks@one-eyed-alien.net> Date: Mon Jan 27 22:53:57 2014 +0000 Move mtree.5 to usr.sbin/nmtree. Remove note that mtree 2.0 format files aren't supported. Sponsored by: DARPA, AFRL 262648 Sat Mar 01 01:48:01 MST 2014 brooks MFC: 261298 Merge from CheriBSD: commit 70b8f0c127db6b80411789d237b403cc64a93573 Author: Brooks Davis <brooks@one-eyed-alien.net> Date: Mon Jan 27 22:53:57 2014 +0000 Move mtree.5 to usr.sbin/nmtree. Remove note that mtree 2.0 format files aren't supported. Sponsored by: DARPA, AFRL |
| /freebsd-10-stable/sys/powerpc/powerpc/ | ||
| H A D | fuswintr.c | diff 90643 Wed Feb 13 23:39:11 MST 2002 benno Complete rework of the PowerPC pmap and a number of other bits in the early boot sequence. The new pmap.c is based on NetBSD's newer pmap.c (for the mpc6xx processors) which is 70% faster than the older code that the original pmap.c was based on. It has also been based on the framework established by jake's initial sparc64 pmap.c. There is no change to how far the kernel gets (it makes it to the mountroot prompt in psim) but the new pmap code is a lot cleaner. Obtained from: NetBSD (pmap code) |
| /freebsd-10-stable/sys/amd64/include/ | ||
| H A D | intr_machdep.h | diff 303776 Fri Aug 05 15:28:29 MDT 2016 jhb MFC 302181,302635: Disable MSI-X migration on older Xen hypervisors. 302181: Add a tunable to disable migration of MSI-X interrupts. The new 'machdep.disable_msix_migration' tunable can be set to 1 to disable migration of MSI-X interrupts. Xen versions prior to 4.6.0 do not properly handle updates to MSI-X table entries after the initial write. In particular, the operation to unmask a table entry after updating it during migration is not propagated to the "real" table for passthrough devices causing the interrupt to remain masked. At least some systems in EC2 are affected by this bug when using SRIOV. The tunable can be set in loader.conf as a workaround. 302635: xen: automatically disable MSI-X interrupt migration If the hypervisor version is smaller than 4.6.0. Xen commits 74fd00 and 70a3cb are required on the hypervisor side for this to be fixed, and those are only included in 4.6.0, so stay on the safe side and disable MSI-X interrupt migration on anything older than 4.6.0. It should not cause major performance degradation unless a lot of MSI-X interrupts are allocated. |
| H A D | specialreg.h | diff 210624 Thu Jul 29 17:13:53 MDT 2010 delphij Improve cputemp(4) driver wrt newer Intel processors, especially Xeon 5500/5600 series: - Utilize IA32_TEMPERATURE_TARGET, a.k.a. Tj(target) in place of Tj(max) when a sane value is available, as documented in Intel whitepaper "CPU Monitoring With DTS/PECI"; (By sane value we mean 70C - 100C for now); - Print the probe results when booting verbose; - Replace cpu_mask with cpu_stepping; - Use CPUID_* macros instead of rolling our own. Approved by: rpaulo MFC after: 1 month |
| /freebsd-10-stable/sys/i386/include/ | ||
| H A D | intr_machdep.h | diff 303776 Fri Aug 05 15:28:29 MDT 2016 jhb MFC 302181,302635: Disable MSI-X migration on older Xen hypervisors. 302181: Add a tunable to disable migration of MSI-X interrupts. The new 'machdep.disable_msix_migration' tunable can be set to 1 to disable migration of MSI-X interrupts. Xen versions prior to 4.6.0 do not properly handle updates to MSI-X table entries after the initial write. In particular, the operation to unmask a table entry after updating it during migration is not propagated to the "real" table for passthrough devices causing the interrupt to remain masked. At least some systems in EC2 are affected by this bug when using SRIOV. The tunable can be set in loader.conf as a workaround. 302635: xen: automatically disable MSI-X interrupt migration If the hypervisor version is smaller than 4.6.0. Xen commits 74fd00 and 70a3cb are required on the hypervisor side for this to be fixed, and those are only included in 4.6.0, so stay on the safe side and disable MSI-X interrupt migration on anything older than 4.6.0. It should not cause major performance degradation unless a lot of MSI-X interrupts are allocated. |
| H A D | specialreg.h | diff 210624 Thu Jul 29 17:13:53 MDT 2010 delphij Improve cputemp(4) driver wrt newer Intel processors, especially Xeon 5500/5600 series: - Utilize IA32_TEMPERATURE_TARGET, a.k.a. Tj(target) in place of Tj(max) when a sane value is available, as documented in Intel whitepaper "CPU Monitoring With DTS/PECI"; (By sane value we mean 70C - 100C for now); - Print the probe results when booting verbose; - Replace cpu_mask with cpu_stepping; - Use CPUID_* macros instead of rolling our own. Approved by: rpaulo MFC after: 1 month |
| /freebsd-10-stable/gnu/usr.bin/diff3/ | ||
| H A D | Makefile | 70 Tue Jun 29 06:19:28 MDT 1993 nate GNU3 Diff 2.3 |
| /freebsd-10-stable/usr.sbin/nmtree/ | ||
| H A D | Makefile | diff 262648 Sat Mar 01 01:48:01 MST 2014 brooks MFC: 261298 Merge from CheriBSD: commit 70b8f0c127db6b80411789d237b403cc64a93573 Author: Brooks Davis <brooks@one-eyed-alien.net> Date: Mon Jan 27 22:53:57 2014 +0000 Move mtree.5 to usr.sbin/nmtree. Remove note that mtree 2.0 format files aren't supported. Sponsored by: DARPA, AFRL 262648 Sat Mar 01 01:48:01 MST 2014 brooks MFC: 261298 Merge from CheriBSD: commit 70b8f0c127db6b80411789d237b403cc64a93573 Author: Brooks Davis <brooks@one-eyed-alien.net> Date: Mon Jan 27 22:53:57 2014 +0000 Move mtree.5 to usr.sbin/nmtree. Remove note that mtree 2.0 format files aren't supported. Sponsored by: DARPA, AFRL |
| /freebsd-10-stable/sys/x86/xen/ | ||
| H A D | hvm.c | diff 303776 Fri Aug 05 15:28:29 MDT 2016 jhb MFC 302181,302635: Disable MSI-X migration on older Xen hypervisors. 302181: Add a tunable to disable migration of MSI-X interrupts. The new 'machdep.disable_msix_migration' tunable can be set to 1 to disable migration of MSI-X interrupts. Xen versions prior to 4.6.0 do not properly handle updates to MSI-X table entries after the initial write. In particular, the operation to unmask a table entry after updating it during migration is not propagated to the "real" table for passthrough devices causing the interrupt to remain masked. At least some systems in EC2 are affected by this bug when using SRIOV. The tunable can be set in loader.conf as a workaround. 302635: xen: automatically disable MSI-X interrupt migration If the hypervisor version is smaller than 4.6.0. Xen commits 74fd00 and 70a3cb are required on the hypervisor side for this to be fixed, and those are only included in 4.6.0, so stay on the safe side and disable MSI-X interrupt migration on anything older than 4.6.0. It should not cause major performance degradation unless a lot of MSI-X interrupts are allocated. |
| /freebsd-10-stable/sys/powerpc/include/ | ||
| H A D | sr.h | 90643 Wed Feb 13 23:39:11 MST 2002 benno Complete rework of the PowerPC pmap and a number of other bits in the early boot sequence. The new pmap.c is based on NetBSD's newer pmap.c (for the mpc6xx processors) which is 70% faster than the older code that the original pmap.c was based on. It has also been based on the framework established by jake's initial sparc64 pmap.c. There is no change to how far the kernel gets (it makes it to the mountroot prompt in psim) but the new pmap code is a lot cleaner. Obtained from: NetBSD (pmap code) |
| H A D | pte.h | diff 90643 Wed Feb 13 23:39:11 MST 2002 benno Complete rework of the PowerPC pmap and a number of other bits in the early boot sequence. The new pmap.c is based on NetBSD's newer pmap.c (for the mpc6xx processors) which is 70% faster than the older code that the original pmap.c was based on. It has also been based on the framework established by jake's initial sparc64 pmap.c. There is no change to how far the kernel gets (it makes it to the mountroot prompt in psim) but the new pmap code is a lot cleaner. Obtained from: NetBSD (pmap code) |
| H A D | md_var.h | diff 90643 Wed Feb 13 23:39:11 MST 2002 benno Complete rework of the PowerPC pmap and a number of other bits in the early boot sequence. The new pmap.c is based on NetBSD's newer pmap.c (for the mpc6xx processors) which is 70% faster than the older code that the original pmap.c was based on. It has also been based on the framework established by jake's initial sparc64 pmap.c. There is no change to how far the kernel gets (it makes it to the mountroot prompt in psim) but the new pmap code is a lot cleaner. Obtained from: NetBSD (pmap code) |
| /freebsd-10-stable/sys/dev/coretemp/ | ||
| H A D | coretemp.c | diff 210624 Thu Jul 29 17:13:53 MDT 2010 delphij Improve cputemp(4) driver wrt newer Intel processors, especially Xeon 5500/5600 series: - Utilize IA32_TEMPERATURE_TARGET, a.k.a. Tj(target) in place of Tj(max) when a sane value is available, as documented in Intel whitepaper "CPU Monitoring With DTS/PECI"; (By sane value we mean 70C - 100C for now); - Print the probe results when booting verbose; - Replace cpu_mask with cpu_stepping; - Use CPUID_* macros instead of rolling our own. Approved by: rpaulo MFC after: 1 month |
| /freebsd-10-stable/sys/powerpc/aim/ | ||
| H A D | locore.S | diff 90643 Wed Feb 13 23:39:11 MST 2002 benno Complete rework of the PowerPC pmap and a number of other bits in the early boot sequence. The new pmap.c is based on NetBSD's newer pmap.c (for the mpc6xx processors) which is 70% faster than the older code that the original pmap.c was based on. It has also been based on the framework established by jake's initial sparc64 pmap.c. There is no change to how far the kernel gets (it makes it to the mountroot prompt in psim) but the new pmap code is a lot cleaner. Obtained from: NetBSD (pmap code) |
| H A D | locore32.S | diff 90643 Wed Feb 13 23:39:11 MST 2002 benno Complete rework of the PowerPC pmap and a number of other bits in the early boot sequence. The new pmap.c is based on NetBSD's newer pmap.c (for the mpc6xx processors) which is 70% faster than the older code that the original pmap.c was based on. It has also been based on the framework established by jake's initial sparc64 pmap.c. There is no change to how far the kernel gets (it makes it to the mountroot prompt in psim) but the new pmap code is a lot cleaner. Obtained from: NetBSD (pmap code) |
| H A D | locore64.S | diff 90643 Wed Feb 13 23:39:11 MST 2002 benno Complete rework of the PowerPC pmap and a number of other bits in the early boot sequence. The new pmap.c is based on NetBSD's newer pmap.c (for the mpc6xx processors) which is 70% faster than the older code that the original pmap.c was based on. It has also been based on the framework established by jake's initial sparc64 pmap.c. There is no change to how far the kernel gets (it makes it to the mountroot prompt in psim) but the new pmap code is a lot cleaner. Obtained from: NetBSD (pmap code) |
| /freebsd-10-stable/sys/dev/ath/ath_hal/ar5212/ | ||
| H A D | ar5212_xmit.c | diff 225820 Wed Sep 28 01:17:22 MDT 2011 adrian Change the default CABQ time to be 70% of the beacon interval, rather than the whole beacon interval. The reference driver and Linux ath9k both choose 80% of the beacon interval and they do it in the driver rather than the HAL (Ath reference) or ath9k_hw (ath9k.) This quietens stuck beacon conditions on my AR9220/AR9280 based NICs when a lot of burst broadcast/multicast traffic is going on. It doesn't seem to annoy the earlier MACs as much as the AR9280 and later one. Obtained from: Linux ath9k, Atheros |
| /freebsd-10-stable/sys/geom/journal/ | ||
| H A D | g_journal.c | diff 231075 Mon Feb 06 09:05:29 MST 2012 kib Current implementations of sync(2) and syncer vnode fsync() VOP uses mnt_noasync counter to temporary remove MNTK_ASYNC mount option, which is needed to guarantee a synchronous completion of the initiated i/o before syscall or VOP return. Global removal of MNTK_ASYNC option is harmful because not only i/o started from corresponding thread becomes synchronous, but all i/o is synchronous on the filesystem which is initiated during sync(2) or syncer activity. Instead of removing MNTK_ASYNC from mnt_kern_flag, provide a local thread flag to disable async i/o for current thread only. Use the opportunity to move DOINGASYNC() macro into sys/vnode.h and consistently use it through places which tested for MNTK_ASYNC. Some testing demonstrated 60-70% improvements in run time for the metadata-intensive operations on async-mounted UFS volumes, but still with great deviation due to other reasons. Reviewed by: mckusick Tested by: scottl MFC after: 2 weeks |
| /freebsd-10-stable/usr.sbin/cxgbetool/ | ||
| H A D | cxgbetool.c | diff 269106 Sat Jul 26 01:00:50 MDT 2014 np Add a 'raw' parameter to the 'modinfo' subcommand. This is handy when trying to figure out why a QSFP+/SFP+ connector or cable wasn't identified correctly by cxgbe(4). Its output looks like this: # cxgbetool t5nex0 modinfo 0 raw 00: 03 04 21 00 00 00 00 00 ..!. .... 08: 04 00 00 00 67 00 00 00 .... g... 10: 00 00 05 00 41 6d 70 68 .... Amph 18: 65 6e 6f 6c 20 20 20 20 enol 20: 20 20 20 20 00 41 50 48 .APH 28: 35 37 31 35 34 30 30 30 5715 4000 30: 33 20 20 20 20 20 20 20 3 38: 4b 20 20 20 01 00 00 fa K .... 40: 00 00 00 00 41 50 46 31 .... APF1 48: 30 30 34 30 30 33 30 30 0040 0300 50: 30 33 20 20 31 30 30 31 03 1001 58: 33 30 20 20 00 00 00 97 30 .... MFC after: 3 days |
| /freebsd-10-stable/sys/x86/x86/ | ||
| H A D | msi.c | diff 303776 Fri Aug 05 15:28:29 MDT 2016 jhb MFC 302181,302635: Disable MSI-X migration on older Xen hypervisors. 302181: Add a tunable to disable migration of MSI-X interrupts. The new 'machdep.disable_msix_migration' tunable can be set to 1 to disable migration of MSI-X interrupts. Xen versions prior to 4.6.0 do not properly handle updates to MSI-X table entries after the initial write. In particular, the operation to unmask a table entry after updating it during migration is not propagated to the "real" table for passthrough devices causing the interrupt to remain masked. At least some systems in EC2 are affected by this bug when using SRIOV. The tunable can be set in loader.conf as a workaround. 302635: xen: automatically disable MSI-X interrupt migration If the hypervisor version is smaller than 4.6.0. Xen commits 74fd00 and 70a3cb are required on the hypervisor side for this to be fixed, and those are only included in 4.6.0, so stay on the safe side and disable MSI-X interrupt migration on anything older than 4.6.0. It should not cause major performance degradation unless a lot of MSI-X interrupts are allocated. |
| /freebsd-10-stable/sys/amd64/amd64/ | ||
| H A D | prof_machdep.c | diff 174067 Thu Nov 29 00:01:21 MST 2007 bde Don't use plain "ret" instructions at targets of jump instructions, since the branch caches on at least Athlon XP through Athlon 64 CPU's don't understand such instructions and guarantee a cache miss taking at least 10 cycles. Use the documented workaround "ret $0" instead ("nop; ret" also works, but "ret $0" is probably faster on old CPUs). Normal code (even asm code) doesn't branch to "ret", since there is usually some cleanup to do, but the __mcount, .mcount and .mexitcount entry points were optimized too well to have the minimum number of instructions (3 instructions each if profiling is not enabled) and they did this. I didn't see a significant number of cache misses for .mexitcount, but for the shared "ret" for __mcount and .mcount I observed cache misses costing 26 cycles each. For a send(2) syscall that makes about 70 function calls, the cost of these cache misses alone increased the syscall time from about 4000 cycles to about 7000 cycles. 4000 is for a profiling (GUPROF) kernel with profiling disabled; after this fix, configuring profiling only costs about 600 cycles in the 4000, which is consistent with almost perfect branch prediction in the mcounting calls. |
| /freebsd-10-stable/sys/dev/ath/ath_hal/ar5416/ | ||
| H A D | ar5416_xmit.c | diff 225820 Wed Sep 28 01:17:22 MDT 2011 adrian Change the default CABQ time to be 70% of the beacon interval, rather than the whole beacon interval. The reference driver and Linux ath9k both choose 80% of the beacon interval and they do it in the driver rather than the HAL (Ath reference) or ath9k_hw (ath9k.) This quietens stuck beacon conditions on my AR9220/AR9280 based NICs when a lot of burst broadcast/multicast traffic is going on. It doesn't seem to annoy the earlier MACs as much as the AR9280 and later one. Obtained from: Linux ath9k, Atheros |
| /freebsd-10-stable/sys/dev/ste/ | ||
| H A D | if_stereg.h | diff 200950 Thu Dec 24 15:33:57 MST 2009 yongari Implement RX interrupt moderation using one-shot timer interrupt. Unlike TX interrupt, ST201 does not provide any mechanism to suppress RX interrupts. ste(4) can generate more than 70k RX interrupts under heavy RX traffics such that these excessive interrupts make system useless to process other useful things. Maybe this was the major reason why polling support code was introduced to ste(4). The STE_COUNTDOWN register provides a programmable counter that will generate an interrupt upon its expiration. We program STE_DMACTL register to use 3.2us clock rate to drive the counter register. Whenever ste(4) serves RX interrupt, the driver rearm the timer to expire after STE_IM_RX_TIMER_DEFAULT time and disables further generation of RX interrupts. This trick seems to work well and ste(4) generates less than 8k RX interrupts even under 64 bytes UDP torture test. Combined with TX interrupts, the total number of interrupts are less than 10k which looks reasonable on heavily loaded controller. The default RX interrupt moderation time is 150us. Users can change the value at any time with dev.ste.%d.int_rx_mod sysctl node. Setting it 0 effectively disables the RX interrupt moderation feature. Now we have both TX/RX interrupt moderation code so remove loop of interrupt handler which resulted in sub-optimal performance as well as more register accesses. |
| /freebsd-10-stable/sys/i386/isa/ | ||
| H A D | prof_machdep.c | diff 174067 Thu Nov 29 00:01:21 MST 2007 bde Don't use plain "ret" instructions at targets of jump instructions, since the branch caches on at least Athlon XP through Athlon 64 CPU's don't understand such instructions and guarantee a cache miss taking at least 10 cycles. Use the documented workaround "ret $0" instead ("nop; ret" also works, but "ret $0" is probably faster on old CPUs). Normal code (even asm code) doesn't branch to "ret", since there is usually some cleanup to do, but the __mcount, .mcount and .mexitcount entry points were optimized too well to have the minimum number of instructions (3 instructions each if profiling is not enabled) and they did this. I didn't see a significant number of cache misses for .mexitcount, but for the shared "ret" for __mcount and .mcount I observed cache misses costing 26 cycles each. For a send(2) syscall that makes about 70 function calls, the cost of these cache misses alone increased the syscall time from about 4000 cycles to about 7000 cycles. 4000 is for a profiling (GUPROF) kernel with profiling disabled; after this fix, configuring profiling only costs about 600 cycles in the 4000, which is consistent with almost perfect branch prediction in the mcounting calls. |
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