| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 94 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { argument
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| H A D | TargetInstrInfo.cpp | 175 Register Reg1 = MI.getOperand(Idx1).getReg(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 164 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
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| H A D | X86AvoidStoreForwardingBlocks.cpp | 395 Register Reg1 = MRI->createVirtualRegister( local
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| H A D | X86MCInstLower.cpp | 2056 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1); local
2087 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 98 bool contains(unsigned Reg1, unsigned Reg2) const { argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 447 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) argument
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| H A D | Thumb2SizeReduction.cpp | 747 Register Reg1 = MI->getOperand(1).getReg(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); variable
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.cpp | 275 adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const argument
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| H A D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { argument
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| H A D | MipsSEFrameLowering.cpp | 465 unsigned Reg1 = local
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; local
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| H A D | MipsAsmPrinter.cpp | 874 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) argument
894 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument
905 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 872 Register Reg1 = MI->getOperand(1).getReg(); local
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| H A D | PPCRegisterInfo.cpp | 668 unsigned Reg1 = Reg; local
713 unsigned Reg1 = Reg; local
817 unsigned Reg1 = Reg; local
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| H A D | PPCInstrInfo.cpp | 396 Register Reg1 = MI.getOperand(1).getReg(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.cpp | 99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); local
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| H A D | MipsTargetStreamer.cpp | 190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
242 emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 783 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, unsigned VM, bool Compr, unsigned Enabled, bool Done) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { argument
740 uint16_t Reg1 = 0; member in class:llvm::MCRegUnitRootIterator
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 968 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCDwarf.cpp | 1335 unsigned Reg1 = Instr.getRegister(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, argument
900 Register Reg1, Reg2; local
1214 Register Reg1, Reg2; local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 524 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); local
537 Register Reg1 = MBBI->getOperand(2).getReg(); local
575 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); local
586 Register Reg1 = MBBI->getOperand(1).getReg(); local
1873 invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, bool NeedsWinCFI) argument
1896 invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, bool UsesWinAAPCS, bool NeedsWinCFI, bool NeedsFrameRecord) argument
1912 unsigned Reg1 = AArch64::NoRegister; member in struct:__anon92::RegPairInfo
2137 unsigned Reg1 = RPI.Reg1; local
[all...] |