| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyReplacePhysRegs.cpp | 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); local
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| H A D | WebAssemblyRegColoring.cpp | 140 const TargetRegisterClass *RC = MRI->getRegClass(Old); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveStacks.cpp | 57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
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| H A D | AggressiveAntiDepBreaker.h | 48 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::RegisterReference
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| H A D | RegisterClassInfo.cpp | 170 const TargetRegisterClass *RC = nullptr; local
[all...] |
| H A D | MIRVRegNamerUtils.cpp | 153 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 28 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument
72 getNVPTXRegClassStr(TargetRegisterClass const *RC) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 88 const auto RC = MRI.getRegClass(Reg); local
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| H A D | AMDGPUISelLowering.h | 282 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
289 CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelector.cpp | 36 constrainOperandRegToRegClass( MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const argument
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| H A D | InstructionSelect.cpp | 200 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); local
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| H A D | RegisterBank.cpp | 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); local
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupSetCC.cpp | 102 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() local
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| /freebsd-11-stable/crypto/openssl/crypto/whrlpool/ |
| H A D | wp_block.c | 461 #define RC (&(Cx.q[256*N])) macro
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 72 const TargetRegisterClass *RC; local
153 const TargetRegisterClass &RC = local
168 const TargetRegisterClass &RC = Mips::GPR32RegClass; local
192 getMoveF64ViaSpillFI(const TargetRegisterClass *RC) argument
[all...] |
| H A D | Mips16RegisterInfo.cpp | 56 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
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| H A D | MipsRegisterInfo.cpp | 67 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC; member in struct:__anon3383::InstructionMemo
41 InstructionMemo(StringRef Name, const CodeGenRegisterClass *RC, argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64DeadRegisterDefinitionsPass.cpp | 160 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); local
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| H A D | AArch64RegisterInfo.cpp | 103 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 78 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
106 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRAsmPrinter.cpp | 111 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | BitTracker.cpp | 115 raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { argument
165 OS << "]:" << RC[Start]; local
201 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigne argument
214 insert(const BT::RegisterCell &RC, const BitMask &M) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 51 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument
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