clk/imx/clk-imx6q.c

42 	void *base;
45 	base = (void *)ANATOP_BASE_ADDR;
49 			     base + 0x30, 0x1));
52 			     base + 0x10, 0x3));
56 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
58 	       imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
60 	       imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
62 	       imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
65 	base = dev_read_addr_ptr(dev);
66 	if (!base)
70 	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
73 	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
76 	       imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
79 	       imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
84 			       base + 0x24, 11, 3));
87 			       base + 0x24, 16, 3));
90 			       base + 0x24, 19, 3));
93 			       base + 0x24, 22, 3));
96 	       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
99 	       imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
101 	       imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
103 	       imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
105 	       imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
107 	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
109 	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
111 	       imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
113 	       imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
116 	       imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
119 	       imx_clk_busy_mux("periph",  base + 0x14, 25, 1, base + 0x48,
122 	       imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
123 				    base + 0x48, 1));
125 	       imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
127 	       imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
129 	       imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
131 	       imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
133 	clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));