intel/int340x_thermal/processor_thermal_device_pci.c

69 static void proc_thermal_mmio_read(struct proc_thermal_pci *pci_info,
73 	*value = ioread32(((u8 __iomem *)pci_info->proc_priv->mmio_base +
79 static void proc_thermal_mmio_write(struct proc_thermal_pci *pci_info,
86 	current_val = ioread32(((u8 __iomem *)pci_info->proc_priv->mmio_base +
95 	iowrite32(current_val, ((u8 __iomem *)pci_info->proc_priv->mmio_base +
107 	struct proc_thermal_pci *pci_info = container_of(delayed_work,
109 	struct thermal_zone_device *tzone = pci_info->tzone;
115 	proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_INT_ENABLE_0, 1);
140 	struct proc_thermal_pci *pci_info = devid;
142 	proc_thermal_wt_intr_callback(pci_info->pdev, pci_info->proc_priv);
143 	proc_thermal_power_floor_intr_callback(pci_info->pdev, pci_info->proc_priv);
144 	proc_thermal_clear_soc_int_status(pci_info->proc_priv);
151 	struct proc_thermal_pci *pci_info = devid;
156 	proc_priv = pci_info->proc_priv;
159 		if (proc_thermal_check_wt_intr(pci_info->proc_priv))
164 		if (proc_thermal_check_power_floor_intr(pci_info->proc_priv))
173 	proc_thermal_mmio_read(pci_info, PROC_THERMAL_MMIO_INT_STATUS_0, &status);
176 		proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_INT_ENABLE_0, 0);
177 		pkg_thermal_schedule_work(&pci_info->work);
180 	pci_write_config_byte(pci_info->pdev, 0xdc, 0x01);
187 	struct proc_thermal_pci *pci_info = thermal_zone_device_priv(tzd);
190 	proc_thermal_mmio_read(pci_info, PROC_THERMAL_MMIO_PKG_TEMP, &_temp);
198 	struct proc_thermal_pci *pci_info = thermal_zone_device_priv(tzd);
202 		cancel_delayed_work_sync(&pci_info->work);
203 		proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_INT_ENABLE_0, 0);
204 		proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_THRES_0, 0);
205 		pci_info->stored_thres = 0;
209 	proc_thermal_mmio_read(pci_info, PROC_THERMAL_MMIO_TJMAX, &tjmax);
214 	proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_THRES_0, _temp);
215 	proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_INT_ENABLE_0, 1);
217 	pci_info->stored_thres = temp;
222 static int get_trip_temp(struct proc_thermal_pci *pci_info)
226 	proc_thermal_mmio_read(pci_info, PROC_THERMAL_MMIO_THRES_0, &temp);
230 	proc_thermal_mmio_read(pci_info, PROC_THERMAL_MMIO_TJMAX, &tjmax);
249 	struct proc_thermal_pci *pci_info;
261 	pci_info = devm_kzalloc(&pdev->dev, sizeof(*pci_info), GFP_KERNEL);
262 	if (!pci_info)
265 	pci_info->pdev = pdev;
274 	INIT_DELAYED_WORK(&pci_info->work, proc_thermal_threshold_work_fn);
276 	proc_priv->priv_data = pci_info;
277 	pci_info->proc_priv = proc_priv;
287 		pci_info->no_legacy = 1;
290 	psv_trip.temperature = get_trip_temp(pci_info);
292 	pci_info->tzone = thermal_zone_device_register_with_trips("TCPU_PCI", &psv_trip,
293 							1, pci_info,
296 	if (IS_ERR(pci_info->tzone)) {
297 		ret = PTR_ERR(pci_info->tzone);
318 					irq_flag, KBUILD_MODNAME, pci_info);
324 	ret = thermal_zone_device_enable(pci_info->tzone);
334 	thermal_zone_device_unregister(pci_info->tzone);
336 	if (!pci_info->no_legacy)
347 	struct proc_thermal_pci *pci_info = proc_priv->priv_data;
349 	cancel_delayed_work_sync(&pci_info->work);
351 	proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_THRES_0, 0);
352 	proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_INT_ENABLE_0, 0);
354 	devm_free_irq(&pdev->dev, pdev->irq, pci_info);
357 	thermal_zone_device_unregister(pci_info->tzone);
358 	proc_thermal_mmio_remove(pdev, pci_info->proc_priv);
359 	if (!pci_info->no_legacy)
369 	struct proc_thermal_pci *pci_info;
372 	pci_info = proc_priv->priv_data;
374 	if (!pci_info->no_legacy)
383 	struct proc_thermal_pci *pci_info;
386 	pci_info = proc_priv->priv_data;
388 	if (pci_info->stored_thres) {
389 		proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_THRES_0,
390 					 pci_info->stored_thres / 1000);
391 		proc_thermal_mmio_write(pci_info, PROC_THERMAL_MMIO_INT_ENABLE_0, 1);
394 	if (!pci_info->no_legacy)