subdev/bar/nv50.c

34 	struct nv50_bar *bar = nv50_bar(base);
35 	struct nvkm_device *device = bar->base.subdev.device;
37 	spin_lock_irqsave(&bar->base.lock, flags);
43 	spin_unlock_irqrestore(&bar->base.lock, flags);
59 nv50_bar_bar1_fini(struct nvkm_bar *bar)
61 	nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000);
68 	struct nv50_bar *bar = nv50_bar(base);
69 	nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
79 nv50_bar_bar2_fini(struct nvkm_bar *bar)
81 	nvkm_wr32(bar->subdev.device, 0x00170c, 0x00000000);
88 	struct nv50_bar *bar = nv50_bar(base);
89 	nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);
90 	nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);
91 	nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4);
97 	struct nv50_bar *bar = nv50_bar(base);
98 	struct nvkm_device *device = bar->base.subdev.device;
108 	struct nv50_bar *bar = nv50_bar(base);
109 	struct nvkm_device *device = bar->base.subdev.device;
115 	ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);
119 	ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem,
120 			      &bar->pad);
124 	ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd);
136 			   &bar2_lock, "bar2", &bar->bar2_vmm);
140 	atomic_inc(&bar->bar2_vmm->engref[NVKM_SUBDEV_BAR]);
141 	bar->bar2_vmm->debug = bar->base.subdev.debug;
143 	ret = nvkm_vmm_boot(bar->bar2_vmm);
147 	ret = nvkm_vmm_join(bar->bar2_vmm, bar->mem->memory);
151 	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2);
155 	nvkm_kmap(bar->bar2);
156 	nvkm_wo32(bar->bar2, 0x00, 0x7fc00000);
157 	nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit));
158 	nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start));
159 	nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 |
161 	nvkm_wo32(bar->bar2, 0x10, 0x00000000);
162 	nvkm_wo32(bar->bar2, 0x14, 0x00000000);
163 	nvkm_done(bar->bar2);
165 	bar->base.subdev.oneinit = true;
176 			   &bar1_lock, "bar1", &bar->bar1_vmm);
180 	atomic_inc(&bar->bar1_vmm->engref[NVKM_SUBDEV_BAR]);
181 	bar->bar1_vmm->debug = bar->base.subdev.debug;
183 	ret = nvkm_vmm_join(bar->bar1_vmm, bar->mem->memory);
187 	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1);
191 	nvkm_kmap(bar->bar1);
192 	nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);
193 	nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));
194 	nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));
195 	nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |
197 	nvkm_wo32(bar->bar1, 0x10, 0x00000000);
198 	nvkm_wo32(bar->bar1, 0x14, 0x00000000);
199 	nvkm_done(bar->bar1);
206 	struct nv50_bar *bar = nv50_bar(base);
207 	if (bar->mem) {
208 		nvkm_gpuobj_del(&bar->bar1);
209 		nvkm_vmm_part(bar->bar1_vmm, bar->mem->memory);
210 		nvkm_vmm_unref(&bar->bar1_vmm);
211 		nvkm_gpuobj_del(&bar->bar2);
212 		nvkm_vmm_part(bar->bar2_vmm, bar->mem->memory);
213 		nvkm_vmm_unref(&bar->bar2_vmm);
214 		nvkm_gpuobj_del(&bar->pgd);
215 		nvkm_gpuobj_del(&bar->pad);
216 		nvkm_gpuobj_del(&bar->mem);
218 	return bar;
225 	struct nv50_bar *bar;
226 	if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))
228 	nvkm_bar_ctor(func, device, type, inst, &bar->base);
229 	bar->pgd_addr = pgd_addr;
230 	*pbar = &bar->base;