Lines Matching refs:cmd
2018 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
2022 "%s: could not allocate TX cmd DMA memory, error %d\n",
2951 * which is done with a firmware cmd. We also defer
3479 "%s: received statistics, cmd %d, len %d\n",
4554 struct iwn_tx_cmd *cmd;
4715 cmd = &ring->cmd[ring->cur];
4716 tx = (struct iwn_cmd_data *)cmd->data;
4765 struct iwn_tx_cmd *cmd;
4815 cmd = &ring->cmd[ring->cur];
4817 tx = (struct iwn_cmd_data *)cmd->data;
4856 struct iwn_tx_cmd *cmd;
4881 cmd = &ring->cmd[ring->cur];
4882 cmd->code = IWN_CMD_TX_DATA;
4883 cmd->flags = 0;
4884 cmd->qid = ring->qid;
4885 cmd->idx = ring->cur;
4887 tx = (struct iwn_cmd_data *)cmd->data;
5170 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
5181 switch (cmd) {
5203 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data)
5246 struct iwn_tx_cmd *cmd;
5267 if (size > sizeof cmd->data) {
5274 cmd = mtod(m, struct iwn_tx_cmd *);
5275 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
5283 cmd = &ring->cmd[ring->cur];
5287 cmd->code = code;
5288 cmd->flags = 0;
5289 cmd->qid = ring->qid;
5290 cmd->idx = ring->cur;
5291 memcpy(cmd->data, buf, size);
5298 __func__, iwn_intr_str(cmd->code), cmd->code,
5299 cmd->flags, cmd->qid, cmd->idx);
5301 if (size > sizeof cmd->data) {
5516 struct iwn_edca_params cmd;
5524 memset(&cmd, 0, sizeof cmd);
5525 cmd.flags = htole32(IWN_EDCA_UPDATE);
5530 cmd.ac[aci].aifsn = ac->wmep_aifsn;
5531 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin));
5532 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax));
5533 cmd.ac[aci].txoplimit =
5539 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1);
5643 struct iwn_cmd_timing cmd;
5648 memset(&cmd, 0, sizeof cmd);
5649 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
5650 cmd.bintval = htole16(ni->ni_intval);
5651 cmd.lintval = htole16(10);
5655 mod = le64toh(cmd.tstamp) % val;
5656 cmd.binitval = htole32((uint32_t)(val - mod));
5659 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
5661 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
5697 struct iwn4965_cmd_txpower cmd;
5711 memset(&cmd, 0, sizeof cmd);
5712 cmd.band = is_chan_5ghz ? 0 : 1;
5713 cmd.chan = chan;
5809 if (cmd.band == 0)
5823 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
5824 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
5830 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
5839 struct iwn5000_cmd_txpower cmd;
5848 memset(&cmd, 0, sizeof cmd);
5849 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
5850 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
5851 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
5860 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async);
6091 struct iwn_phy_calib_gain cmd;
6095 memset(&cmd, 0, sizeof cmd);
6096 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
6100 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6106 struct iwn_phy_calib cmd;
6110 memset(&cmd, 0, sizeof cmd);
6111 cmd.code = sc->reset_noise_gain;
6112 cmd.ngroups = 1;
6113 cmd.isvalid = 1;
6116 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6123 struct iwn_phy_calib_gain cmd;
6134 memset(&cmd, 0, sizeof cmd);
6135 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
6143 cmd.gain[i] = MIN(abs(delta), 3);
6145 cmd.gain[i] |= 1 << 2; /* sign bit */
6150 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
6151 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6158 struct iwn_phy_calib_gain cmd;
6166 memset(&cmd, 0, sizeof cmd);
6167 cmd.code = sc->noise_gain;
6168 cmd.ngroups = 1;
6169 cmd.isvalid = 1;
6179 cmd.gain[i - 1] = MIN(abs(delta), 3);
6181 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
6186 cmd.gain[0], cmd.gain[1], sc->chainmask);
6187 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6348 struct iwn_enhanced_sensitivity_cmd cmd;
6351 memset(&cmd, 0, sizeof cmd);
6353 cmd.which = IWN_SENSITIVITY_WORKTBL;
6355 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
6356 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
6357 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
6358 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
6359 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
6360 cmd.energy_ofdm_th = htole16(62);
6362 cmd.corr_cck_x4 = htole16(calib->cck_x4);
6363 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
6364 cmd.energy_cck = htole16(calib->energy_cck);
6366 cmd.corr_barker = htole16(190);
6367 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc);
6379 cmd.ofdm_det_slope_mrc = htole16(668);
6380 cmd.ofdm_det_icept_mrc = htole16(4);
6381 cmd.ofdm_det_slope = htole16(486);
6382 cmd.ofdm_det_icept = htole16(37);
6383 cmd.cck_det_slope_mrc = htole16(853);
6384 cmd.cck_det_icept_mrc = htole16(4);
6385 cmd.cck_det_slope = htole16(476);
6386 cmd.cck_det_icept = htole16(99);
6388 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1);
6478 struct iwn_pmgt_cmd cmd;
6499 memset(&cmd, 0, sizeof cmd);
6501 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
6503 cmd.flags |= htole16(IWN_PS_FAST_PD);
6507 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
6508 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
6509 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
6517 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
6526 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
6530 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
6536 struct iwn_bluetooth cmd;
6538 memset(&cmd, 0, sizeof cmd);
6539 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
6540 cmd.lead_time = IWN_BT_LEAD_TIME_DEF;
6541 cmd.max_kill = IWN_BT_MAX_KILL_DEF;
6544 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0);
6655 struct iwn5000_calib_config cmd;
6657 memset(&cmd, 0, sizeof cmd);
6658 cmd.ucode.once.enable = 0xffffffff;
6659 cmd.ucode.once.start = IWN5000_CALIB_DC;
6662 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0);
6701 struct iwn4965_rxon_assoc cmd;
6704 cmd.flags = rxon->flags;
6705 cmd.filter = rxon->filter;
6706 cmd.ofdm_mask = rxon->ofdm_mask;
6707 cmd.cck_mask = rxon->cck_mask;
6708 cmd.ht_single_mask = rxon->ht_single_mask;
6709 cmd.ht_dual_mask = rxon->ht_dual_mask;
6710 cmd.rxchain = rxon->rxchain;
6711 cmd.reserved = 0;
6713 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async));
6719 struct iwn5000_rxon_assoc cmd;
6722 cmd.flags = rxon->flags;
6723 cmd.filter = rxon->filter;
6724 cmd.ofdm_mask = rxon->ofdm_mask;
6725 cmd.cck_mask = rxon->cck_mask;
6726 cmd.reserved1 = 0;
6727 cmd.ht_single_mask = rxon->ht_single_mask;
6728 cmd.ht_dual_mask = rxon->ht_dual_mask;
6729 cmd.ht_triple_mask = rxon->ht_triple_mask;
6730 cmd.reserved2 = 0;
6731 cmd.rxchain = rxon->rxchain;
6732 cmd.acquisition = rxon->acquisition;
6733 cmd.reserved3 = 0;
6735 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async));
7775 struct iwn5000_calib_config cmd;
7778 memset(&cmd, 0, sizeof cmd);
7779 cmd.ucode.once.enable = htole32(0xffffffff);
7780 cmd.ucode.once.start = htole32(0xffffffff);
7781 cmd.ucode.once.send = htole32(0xffffffff);
7782 cmd.ucode.flags = htole32(0xffffffff);
7785 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
7863 struct iwn5000_phy_calib_crystal cmd;
7865 memset(&cmd, 0, sizeof cmd);
7866 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
7867 cmd.ngroups = 1;
7868 cmd.isvalid = 1;
7869 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
7870 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
7872 cmd.cap_pin[0], cmd.cap_pin[1]);
7873 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7879 struct iwn5000_phy_calib_temp_offset cmd;
7881 memset(&cmd, 0, sizeof cmd);
7882 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
7883 cmd.ngroups = 1;
7884 cmd.isvalid = 1;
7886 cmd.offset = htole16(sc->eeprom_temp);
7888 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET);
7890 le16toh(cmd.offset));
7891 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7897 struct iwn5000_phy_calib_temp_offsetv2 cmd;
7899 memset(&cmd, 0, sizeof cmd);
7900 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
7901 cmd.ngroups = 1;
7902 cmd.isvalid = 1;
7904 cmd.offset_low = htole16(sc->eeprom_temp);
7905 cmd.offset_high = htole16(sc->eeprom_temp_high);
7907 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET);
7908 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET);
7910 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage);
7914 le16toh(cmd.offset_low),
7915 le16toh(cmd.offset_high),
7916 le16toh(cmd.burnt_voltage_ref));
7918 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7966 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
8031 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
8040 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */