dev/pci/if_iwmreg.h

1227  * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1245  * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1247  * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1641  * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1643  * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1738 /* Tx service channels */
2756  * of the device on the channel. Since the fw supports multiple channels
3688  * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3947  *	other channels as well. This should be to true only in case that the
5413  * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
5420  * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
5441  * @channel_num: num of channels to scan
5442  * @active-dwell: dwell time for active channels
5443  * @passive-dwell: dwell time for passive channels
5445  * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
5593  * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
5595  * @scanned_channels: number of channels scanned (and number of valid results)
5641 /* Bits 26-31 are for num of channels in channel_array */
5678  * @dwell_extended:		default dwell time for channels 1, 6 and 11
5683  * @channel_array:		default supported channels
5775  *      parameters following channels configuration array.
5794  *      parameters following channels configuration array.
5814  * @count: num of channels in scan request
5833  * @extended_dwell: dwell time for channels 1, 6 and 11
5976  * @matching_channels: bitmap of channels that matched, referencing
5977  *	the channels passed in tue scan offload request
6016  * @scanned_channels: number of channels scanned and number of valid elements in
6564  * @cap: capabilities for all channels which matches the MCC
6566  * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6567  *		channels, depending on platform)
6568  * @channels: channel control data map, DWORD for each channel. Only the first
6577 	uint32_t channels[0];
6587  * @cap: capabilities for all channels which matches the MCC
6591  * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6592  *		channels, depending on platform)
6593  * @channels: channel control data map, DWORD for each channel. Only the first
6604 	uint32_t channels[0];
6617  * @cap: capabilities for all channels which matches the MCC
6621  * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6622  *		channels, depending on platform)
6623  * @channels: channel control data map, DWORD for each channel. Only the first
6634 	uint32_t channels[0];