dev/pci/if_iwx.c

837 		uint32_t addr, val;
841 		val = le32toh(dest_v1->reg_ops[i].val);
844 		DPRINTF(("%s: op=%u addr=%u val=%u\n", __func__, op, addr, val));
847 			IWX_WRITE(sc, addr, val);
850 			IWX_SETBITS(sc, addr, (1 << val));
853 			IWX_CLRBITS(sc, addr, (1 << val));
856 			iwx_write_prph(sc, addr, val);
859 			err = iwx_set_bits_prph(sc, addr, (1 << val));
864 			err = iwx_clear_bits_prph(sc, addr, (1 << val));
869 			if (iwx_read_prph(sc, addr) & (1 << val))
1658 iwx_write_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1663 	IWX_WRITE(sc, IWX_HBUS_TARG_PRPH_WDAT, val);
1667 iwx_write_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1670 	iwx_write_prph_unlocked(sc, addr, val);
1674 iwx_write_prph64(struct iwx_softc *sc, uint64_t addr, uint64_t val)
1676 	iwx_write_prph(sc, (uint32_t)addr, val & 0xffffffff);
1677 	iwx_write_prph(sc, (uint32_t)addr + 4, val >> 32);
1693 iwx_write_umac_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1695 	iwx_write_prph_unlocked(sc, addr + sc->sc_umac_prph_offset, val);
1699 iwx_write_umac_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1701 	iwx_write_prph(sc, addr + sc->sc_umac_prph_offset, val);
1731 			uint32_t val = vals ? vals[offs] : 0;
1732 			IWX_WRITE(sc, IWX_HBUS_TARG_MEM_WDAT, val);
1742 iwx_write_mem32(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1744 	return iwx_write_mem(sc, addr, &val, 1);
1811 	uint32_t val;
1814 		val = iwx_read_prph(sc, reg) & mask;
1815 		val |= bits;
1816 		iwx_write_prph(sc, reg, val);
2740 	uint32_t mask, val, reg_val = 0;
2767 	val = IWX_READ(sc, IWX_CSR_HW_IF_CONFIG_REG);
2768 	val &= ~mask;
2769 	val |= reg_val;
2770 	IWX_WRITE(sc, IWX_CSR_HW_IF_CONFIG_REG, val);