Lines Matching refs:dst
96 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__MODIFY(dst, src) \
97 (dst) = ((dst) &\
103 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__SET(dst) \
104 (dst) = ((dst) &\
106 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__CLR(dst) \
107 (dst) = ((dst) &\
120 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__MODIFY(dst, src) \
121 (dst) = ((dst) &\
127 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__SET(dst) \
128 (dst) = ((dst) &\
130 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__CLR(dst) \
131 (dst) = ((dst) &\
144 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__MODIFY(dst, src) \
145 (dst) = ((dst) &\
151 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__SET(dst) \
152 (dst) = ((dst) &\
154 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__CLR(dst) \
155 (dst) = ((dst) &\
181 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MODIFY(dst, src) \
182 (dst) = ((dst) &\
188 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SET(dst) \
189 (dst) = ((dst) &\
191 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__CLR(dst) \
192 (dst) = ((dst) &\
205 #define GREEN_TX_CONTROL_1__GREEN_CASES__MODIFY(dst, src) \
206 (dst) = ((dst) &\
212 #define GREEN_TX_CONTROL_1__GREEN_CASES__SET(dst) \
213 (dst) = ((dst) &\
215 #define GREEN_TX_CONTROL_1__GREEN_CASES__CLR(dst) \
216 (dst) = ((dst) &\
238 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MODIFY(dst, src) \
239 (dst) = ((dst) &\
245 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SET(dst) \
246 (dst) = ((dst) &\
248 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__CLR(dst) \
249 (dst) = ((dst) &\
262 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MODIFY(dst, src) \
263 (dst) = ((dst) &\
280 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MODIFY(dst, src) \
281 (dst) = ((dst) &\
287 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SET(dst) \
288 (dst) = ((dst) &\
290 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__CLR(dst) \
291 (dst) = ((dst) &\
315 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MODIFY(dst, src) \
316 (dst) = ((dst) &\
333 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MODIFY(dst, src) \
334 (dst) = ((dst) &\
351 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MODIFY(dst, src) \
352 (dst) = ((dst) &\
374 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MODIFY(dst, src) \
375 (dst) = ((dst) &\
392 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MODIFY(dst, src) \
393 (dst) = ((dst) &\
410 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MODIFY(dst, src) \
411 (dst) = ((dst) &\
428 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MODIFY(dst, src) \
429 (dst) = ((dst) &\
446 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \
447 (dst) = ((dst) &\
453 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SET(dst) \
454 (dst) = ((dst) &\
456 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__CLR(dst) \
457 (dst) = ((dst) &\
479 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MODIFY(dst, src) \
480 (dst) = ((dst) &\
497 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MODIFY(dst, src) \
498 (dst) = ((dst) &\
515 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MODIFY(dst, src) \
516 (dst) = ((dst) &\
533 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MODIFY(dst, src) \
534 (dst) = ((dst) &\
551 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MODIFY(dst, src) \
552 (dst) = ((dst) &\
569 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MODIFY(dst, src) \
570 (dst) = ((dst) &\
587 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MODIFY(dst, src) \
588 (dst) = ((dst) &\
594 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SET(dst) \
595 (dst) = ((dst) &\
597 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__CLR(dst) \
598 (dst) = ((dst) &\
624 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MODIFY(dst, src) \
625 (dst) = ((dst) &\
642 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MODIFY(dst, src) \
643 (dst) = ((dst) &\
660 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MODIFY(dst, src) \
661 (dst) = ((dst) &\
678 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MODIFY(dst, src) \
679 (dst) = ((dst) &\
696 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MODIFY(dst, src) \
697 (dst) = ((dst) &\
714 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MODIFY(dst, src) \
715 (dst) = ((dst) &\
732 #define BT_COEX_2__RFSAT_RX_RX__MODIFY(dst, src) \
733 (dst) = ((dst) &\
761 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MODIFY(dst, src) \
762 (dst) = ((dst) &\
779 #define BT_COEX_3__RFSAT_BT_RX_SRCH__MODIFY(dst, src) \
780 (dst) = ((dst) &\
797 #define BT_COEX_3__RFSAT_BT_SRCH_RX__MODIFY(dst, src) \
798 (dst) = ((dst) &\
815 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MODIFY(dst, src) \
816 (dst) = ((dst) &\
833 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MODIFY(dst, src) \
834 (dst) = ((dst) &\
851 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MODIFY(dst, src) \
852 (dst) = ((dst) &\
869 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MODIFY(dst, src) \
870 (dst) = ((dst) &\
887 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__MODIFY(dst, src) \
888 (dst) = ((dst) &\
905 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__MODIFY(dst, src) \
906 (dst) = ((dst) &\
923 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MODIFY(dst, src) \
924 (dst) = ((dst) &\
941 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MODIFY(dst, src) \
942 (dst) = ((dst) &\
959 #define BT_COEX_3__BT_RX_FIRPWR_INCR__MODIFY(dst, src) \
960 (dst) = ((dst) &\
988 #define BT_COEX_4__RFGAIN_EQV_LNA_0__MODIFY(dst, src) \
989 (dst) = ((dst) &\
1006 #define BT_COEX_4__RFGAIN_EQV_LNA_1__MODIFY(dst, src) \
1007 (dst) = ((dst) &\
1024 #define BT_COEX_4__RFGAIN_EQV_LNA_2__MODIFY(dst, src) \
1025 (dst) = ((dst) &\
1042 #define BT_COEX_4__RFGAIN_EQV_LNA_3__MODIFY(dst, src) \
1043 (dst) = ((dst) &\
1071 #define BT_COEX_5__RFGAIN_EQV_LNA_4__MODIFY(dst, src) \
1072 (dst) = ((dst) &\
1089 #define BT_COEX_5__RFGAIN_EQV_LNA_5__MODIFY(dst, src) \
1090 (dst) = ((dst) &\
1107 #define BT_COEX_5__RFGAIN_EQV_LNA_6__MODIFY(dst, src) \
1108 (dst) = ((dst) &\
1125 #define BT_COEX_5__RFGAIN_EQV_LNA_7__MODIFY(dst, src) \
1126 (dst) = ((dst) &\
1212 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MODIFY(dst, src) \
1213 (dst) = ((dst) &\
1219 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SET(dst) \
1220 (dst) = ((dst) &\
1222 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__CLR(dst) \
1223 (dst) = ((dst) &\
1242 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MODIFY(dst, src) \
1243 (dst) = ((dst) &\
1249 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SET(dst) \
1250 (dst) = ((dst) &\
1252 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__CLR(dst) \
1253 (dst) = ((dst) &\
1267 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MODIFY(dst, src) \
1268 (dst) = ((dst) &\
1274 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SET(dst) \
1275 (dst) = ((dst) &\
1277 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__CLR(dst) \
1278 (dst) = ((dst) &\
1291 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MODIFY(dst, src) \
1292 (dst) = ((dst) &\
1298 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SET(dst) \
1299 (dst) = ((dst) &\
1301 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__CLR(dst) \
1302 (dst) = ((dst) &\
1315 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MODIFY(dst, src) \
1316 (dst) = ((dst) &\
1342 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MODIFY(dst, src) \
1343 (dst) = ((dst) &\
1349 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SET(dst) \
1350 (dst) = ((dst) &\
1352 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__CLR(dst) \
1353 (dst) = ((dst) &\
1366 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MODIFY(dst, src) \
1367 (dst) = ((dst) &\
1384 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MODIFY(dst, src) \
1385 (dst) = ((dst) &\
1391 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SET(dst) \
1392 (dst) = ((dst) &\
1394 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__CLR(dst) \
1395 (dst) = ((dst) &\
1420 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MODIFY(dst, src) \
1421 (dst) = ((dst) &\
1427 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SET(dst) \
1428 (dst) = ((dst) &\
1430 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__CLR(dst) \
1431 (dst) = ((dst) &\
1452 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MODIFY(dst, src) \
1453 (dst) = ((dst) &\
1459 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SET(dst) \
1460 (dst) = ((dst) &\
1462 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__CLR(dst) \
1463 (dst) = ((dst) &\
1476 #define SEARCH_START_DELAY__RM_HCSD4SVD__MODIFY(dst, src) \
1477 (dst) = ((dst) &\
1483 #define SEARCH_START_DELAY__RM_HCSD4SVD__SET(dst) \
1484 (dst) = ((dst) &\
1486 #define SEARCH_START_DELAY__RM_HCSD4SVD__CLR(dst) \
1487 (dst) = ((dst) &\
1507 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MODIFY(dst, src) \
1508 (dst) = ((dst) &\
1514 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SET(dst) \
1515 (dst) = ((dst) &\
1517 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__CLR(dst) \
1518 (dst) = ((dst) &\
1535 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__MODIFY(dst, src) \
1536 (dst) = ((dst) &\
1560 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MODIFY(dst, src) \
1561 (dst) = ((dst) &\
1567 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SET(dst) \
1568 (dst) = ((dst) &\
1570 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__CLR(dst) \
1571 (dst) = ((dst) &\
1592 #define TX_FORCED_GAIN__FORCED_OB2G__MODIFY(dst, src) \
1593 (dst) = ((dst) &\
1610 #define TX_FORCED_GAIN__FORCED_DB2G__MODIFY(dst, src) \
1611 (dst) = ((dst) &\
1628 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MODIFY(dst, src) \
1629 (dst) = ((dst) &\
1635 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SET(dst) \
1636 (dst) = ((dst) &\
1638 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__CLR(dst) \
1639 (dst) = ((dst) &\
1660 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \
1661 (dst) = ((dst) &\
1667 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \
1668 (dst) = ((dst) &\
1670 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \
1671 (dst) = ((dst) &\
1691 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \
1692 (dst) = ((dst) &\
1698 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \
1699 (dst) = ((dst) &\
1701 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \
1702 (dst) = ((dst) &\
1725 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__MODIFY(dst, src) \
1726 (dst) = ((dst) &\
1758 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__MODIFY(dst, src) \
1759 (dst) = ((dst) &\
1791 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__MODIFY(dst, src) \
1792 (dst) = ((dst) &\
1824 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__MODIFY(dst, src) \
1825 (dst) = ((dst) &\
1857 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__MODIFY(dst, src) \
1858 (dst) = ((dst) &\
1890 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__MODIFY(dst, src) \
1891 (dst) = ((dst) &\
1923 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__MODIFY(dst, src) \
1924 (dst) = ((dst) &\
1956 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__MODIFY(dst, src) \
1957 (dst) = ((dst) &\
1989 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__MODIFY(dst, src) \
1990 (dst) = ((dst) &\
2022 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__MODIFY(dst, src) \
2023 (dst) = ((dst) &\
2055 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__MODIFY(dst, src) \
2056 (dst) = ((dst) &\
2088 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__MODIFY(dst, src) \
2089 (dst) = ((dst) &\
2121 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__MODIFY(dst, src) \
2122 (dst) = ((dst) &\
2154 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__MODIFY(dst, src) \
2155 (dst) = ((dst) &\
2187 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__MODIFY(dst, src) \
2188 (dst) = ((dst) &\
2220 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__MODIFY(dst, src) \
2221 (dst) = ((dst) &\
2253 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__MODIFY(dst, src) \
2254 (dst) = ((dst) &\
2286 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__MODIFY(dst, src) \
2287 (dst) = ((dst) &\
2319 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__MODIFY(dst, src) \
2320 (dst) = ((dst) &\
2352 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__MODIFY(dst, src) \
2353 (dst) = ((dst) &\
2385 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__MODIFY(dst, src) \
2386 (dst) = ((dst) &\
2418 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__MODIFY(dst, src) \
2419 (dst) = ((dst) &\
2451 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__MODIFY(dst, src) \
2452 (dst) = ((dst) &\
2484 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__MODIFY(dst, src) \
2485 (dst) = ((dst) &\
2517 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__MODIFY(dst, src) \
2518 (dst) = ((dst) &\
2550 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__MODIFY(dst, src) \
2551 (dst) = ((dst) &\
2583 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__MODIFY(dst, src) \
2584 (dst) = ((dst) &\
2616 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__MODIFY(dst, src) \
2617 (dst) = ((dst) &\
2649 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__MODIFY(dst, src) \
2650 (dst) = ((dst) &\
2682 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__MODIFY(dst, src) \
2683 (dst) = ((dst) &\
2715 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__MODIFY(dst, src) \
2716 (dst) = ((dst) &\
2748 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__MODIFY(dst, src) \
2749 (dst) = ((dst) &\
2781 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__MODIFY(dst, src) \
2782 (dst) = ((dst) &\
2800 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__MODIFY(dst, src) \
2801 (dst) = ((dst) &\
2819 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__MODIFY(dst, src) \
2820 (dst) = ((dst) &\
2838 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__MODIFY(dst, src) \
2839 (dst) = ((dst) &\
2870 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__MODIFY(dst, src) \
2871 (dst) = ((dst) &\
2888 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__MODIFY(dst, src) \
2889 (dst) = ((dst) &\
2906 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__MODIFY(dst, src) \
2907 (dst) = ((dst) &\
2924 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__MODIFY(dst, src) \
2925 (dst) = ((dst) &\
2942 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__MODIFY(dst, src) \
2943 (dst) = ((dst) &\
2973 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__MODIFY(dst, src) \
2974 (dst) = ((dst) &\
3004 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__MODIFY(dst, src) \
3005 (dst) = ((dst) &\
3035 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__MODIFY(dst, src) \
3036 (dst) = ((dst) &\
3066 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__MODIFY(dst, src) \
3067 (dst) = ((dst) &\
3097 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__MODIFY(dst, src) \
3098 (dst) = ((dst) &\
3128 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__MODIFY(dst, src) \
3129 (dst) = ((dst) &\
3159 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__MODIFY(dst, src) \
3160 (dst) = ((dst) &\
3190 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__MODIFY(dst, src) \
3191 (dst) = ((dst) &\
3221 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__MODIFY(dst, src) \
3222 (dst) = ((dst) &\
3252 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__MODIFY(dst, src) \
3253 (dst) = ((dst) &\
3283 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__MODIFY(dst, src) \
3284 (dst) = ((dst) &\
3314 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__MODIFY(dst, src) \
3315 (dst) = ((dst) &\
3345 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__MODIFY(dst, src) \
3346 (dst) = ((dst) &\
3376 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__MODIFY(dst, src) \
3377 (dst) = ((dst) &\
3407 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__MODIFY(dst, src) \
3408 (dst) = ((dst) &\
3438 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__MODIFY(dst, src) \
3439 (dst) = ((dst) &\
3469 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__MODIFY(dst, src) \
3470 (dst) = ((dst) &\
3500 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__MODIFY(dst, src) \
3501 (dst) = ((dst) &\
3531 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__MODIFY(dst, src) \
3532 (dst) = ((dst) &\
3562 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__MODIFY(dst, src) \
3563 (dst) = ((dst) &\
3593 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__MODIFY(dst, src) \
3594 (dst) = ((dst) &\
3624 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__MODIFY(dst, src) \
3625 (dst) = ((dst) &\
3655 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__MODIFY(dst, src) \
3656 (dst) = ((dst) &\
3686 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__MODIFY(dst, src) \
3687 (dst) = ((dst) &\
3717 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__MODIFY(dst, src) \
3718 (dst) = ((dst) &\
3748 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__MODIFY(dst, src) \
3749 (dst) = ((dst) &\
3779 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__MODIFY(dst, src) \
3780 (dst) = ((dst) &\
3810 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__MODIFY(dst, src) \
3811 (dst) = ((dst) &\
3841 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__MODIFY(dst, src) \
3842 (dst) = ((dst) &\
3872 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__MODIFY(dst, src) \
3873 (dst) = ((dst) &\
3903 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__MODIFY(dst, src) \
3904 (dst) = ((dst) &\
3934 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__MODIFY(dst, src) \
3935 (dst) = ((dst) &\
3962 #define PMU1__PWD__MODIFY(dst, src) \
3963 (dst) = ((dst) &\
3974 #define PMU1__NFDIV__MODIFY(dst, src) \
3975 (dst) = ((dst) &\
3979 #define PMU1__NFDIV__SET(dst) \
3980 (dst) = ((dst) &\
3982 #define PMU1__NFDIV__CLR(dst) \
3983 (dst) = ((dst) &\
3992 #define PMU1__REFV__MODIFY(dst, src) \
3993 (dst) = ((dst) &\
4004 #define PMU1__GM1__MODIFY(dst, src) \
4005 (dst) = ((dst) &\
4016 #define PMU1__CLASSB__MODIFY(dst, src) \
4017 (dst) = ((dst) &\
4030 #define PMU1__CC__MODIFY(dst, src) \
4031 (dst) = ((dst) &\
4042 #define PMU1__RC__MODIFY(dst, src) \
4043 (dst) = ((dst) &\
4054 #define PMU1__RAMPSLOPE__MODIFY(dst, src) \
4055 (dst) = ((dst) &\
4068 #define PMU1__SEGM__MODIFY(dst, src) \
4069 (dst) = ((dst) &\
4080 #define PMU1__USELOCALOSC__MODIFY(dst, src) \
4081 (dst) = ((dst) &\
4087 #define PMU1__USELOCALOSC__SET(dst) \
4088 (dst) = ((dst) &\
4090 #define PMU1__USELOCALOSC__CLR(dst) \
4091 (dst) = ((dst) &\
4104 #define PMU1__FORCEXOSCSTABLE__MODIFY(dst, src) \
4105 (dst) = ((dst) &\
4111 #define PMU1__FORCEXOSCSTABLE__SET(dst) \
4112 (dst) = ((dst) &\
4114 #define PMU1__FORCEXOSCSTABLE__CLR(dst) \
4115 (dst) = ((dst) &\
4124 #define PMU1__SELFB__MODIFY(dst, src) \
4125 (dst) = ((dst) &\
4129 #define PMU1__SELFB__SET(dst) \
4130 (dst) = ((dst) &\
4132 #define PMU1__SELFB__CLR(dst) \
4133 (dst) = ((dst) &\
4142 #define PMU1__FILTERFB__MODIFY(dst, src) \
4143 (dst) = ((dst) &\
4169 #define PMU2__SPARE2__MODIFY(dst, src) \
4170 (dst) = ((dst) &\
4181 #define PMU2__PWDLPO_PWD__MODIFY(dst, src) \
4182 (dst) = ((dst) &\
4188 #define PMU2__PWDLPO_PWD__SET(dst) \
4189 (dst) = ((dst) &\
4191 #define PMU2__PWDLPO_PWD__CLR(dst) \
4192 (dst) = ((dst) &\
4201 #define PMU2__DISC_OVR__MODIFY(dst, src) \
4202 (dst) = ((dst) &\
4208 #define PMU2__DISC_OVR__SET(dst) \
4209 (dst) = ((dst) &\
4211 #define PMU2__DISC_OVR__CLR(dst) \
4212 (dst) = ((dst) &\
4221 #define PMU2__PGM__MODIFY(dst, src) \
4222 (dst) = ((dst) &\
4226 #define PMU2__PGM__SET(dst) \
4227 (dst) = ((dst) &\
4229 #define PMU2__PGM__CLR(dst) \
4230 (dst) = ((dst) &\
4239 #define PMU2__FILTERVC__MODIFY(dst, src) \
4240 (dst) = ((dst) &\
4253 #define PMU2__DISC__MODIFY(dst, src) \
4254 (dst) = ((dst) &\
4258 #define PMU2__DISC__SET(dst) \
4259 (dst) = ((dst) &\
4261 #define PMU2__DISC__CLR(dst) \
4262 (dst) = ((dst) &\
4271 #define PMU2__DISCDEL__MODIFY(dst, src) \
4272 (dst) = ((dst) &\
4285 #define PMU2__SPARE1__MODIFY(dst, src) \
4286 (dst) = ((dst) &\