Lines Matching refs:to
4 * Permission to use, copy, modify, and/or distribute this software for any
29 #error AH_BYTE_ORDER needs to be defined!
78 // Add additional definitions to the end.
171 /* Delta from which to start power to pdadc table */
240 u_int16_t reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
247 int8_t pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
251 //bit2 - enable fastClock - default to 1
252 //bit3 - enable doubling - default to 1
253 //bit4 - enable internal regulator - default to 1
254 //bit5 - enable paprd - default to 0
255 //bit6 - enable TuningCaps - default to 0
256 //bit7 - enable tx_frame_to_xpa_on - default to 0
258 // bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermometer 2
259 // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates
296 //Note the order of the fields in this structure has been optimized to put all fields likely to change together
327 // last 12 bytes stolen and moved to newly created base extension structure
334 int8_t rx_noisefloor_cal; /*range is -60 to -127 create a mapping equation 1db resolution */
411 ** used to read EEPROM data, which is apparently stored in little