Lines Matching defs:bit
1424 * Starting with the 82571 chip, bit 31 should be used to
1841 /* Check if we must disable SPEED_MODE bit on PCI-E */
1990 /* check for 64bit BAR */
2045 * Set the bit to enable interrupt
2072 * Set the bit to enable interrupt
2616 * drained a bit. Here we use an arbitrary value of 1500 which will
3082 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3428 u32 index, bit;
3431 bit = vtag & 0x1F;
3432 sc->shadow_vfta[index] |= (1 << bit);
3441 u32 index, bit;
3444 bit = vtag & 0x1F;
3445 sc->shadow_vfta[index] &= ~(1 << bit);
3673 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3699 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
4007 printf("Could not set PHY Host Wakeup bit\n");
4106 /* For the 64-bit byte counters the low dword must be read first. */
4203 /* Export a single 32-bit register via a read-only sysctl. */
4640 * first 32 16-bit words of the EEPROM to
4657 /* Its a bit crude, but it gets the job done */