Lines Matching refs:info
47 mapAtomBIOSACPI(radeon_info &info, uint32& romSize)
73 if (info.pci->vendor_id != vhdr->VendorID || info.pci->device_id != vhdr->DeviceID
74 || info.pci->bus != vhdr->PCIBus || info.pci->device != vhdr->PCIDevice
75 || info.pci->function != vhdr->PCIFunction) {
95 info.rom_area = create_area("radeon hd AtomBIOS",
96 (void**)&info.atom_buffer, B_ANY_KERNEL_ADDRESS,
100 if (info.rom_area < 0) {
107 memset((void*)info.atom_buffer, 0, areaSize);
109 memcpy(info.atom_buffer, (void*)rom, romSize);
113 romHeader = RADEON_BIOS16(info.atom_buffer, 0x48);
114 romValid = !memcmp(&info.atom_buffer[romHeader + 4], "ATOM", 4)
115 || !memcmp(&info.atom_buffer[romHeader + 4], "MOTA", 4);
118 set_area_protection(info.rom_area,
157 mapAtomBIOS(radeon_info &info, phys_addr_t romBase, uint32 romSize,
199 info.rom_area = create_area("radeon hd AtomBIOS",
200 (void**)&info.atom_buffer, B_ANY_KERNEL_ADDRESS,
204 if (info.rom_area < 0) {
211 memset((void*)info.atom_buffer, 0, romSize);
221 memcpy(info.atom_buffer, (void*)rom, romSize);
225 romHeader = RADEON_BIOS16(info.atom_buffer, 0x48);
226 romValid = !memcmp(&info.atom_buffer[romHeader + 4], "ATOM", 4)
227 || !memcmp(&info.atom_buffer[romHeader + 4], "MOTA", 4);
230 set_area_protection(info.rom_area,
242 radeon_hd_getbios(radeon_info &info)
244 TRACE("card(%" B_PRId32 "): %s: called\n", info.id, __func__);
257 mapResult = mapAtomBIOSACPI(info, romSize);
263 romBase = info.pci->u.h0.base_registers[PCI_BAR_FB];
264 if ((info.pci->u.h0.base_register_flags[PCI_BAR_FB] & PCI_address_type)
266 romBase |= (uint64)info.pci->u.h0.base_registers[PCI_BAR_FB + 1] << 32;
273 mapResult = mapAtomBIOS(info, romBase, romSize);
280 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4);
282 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
284 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4);
288 romBase = info.pci->u.h0.rom_base;
289 romSize = info.pci->u.h0.rom_size;
294 mapResult = mapAtomBIOS(info, romBase, romSize, true);
299 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
315 info.shared_info->rom_phys = romBase;
316 info.shared_info->rom_size = romSize;
325 radeon_hd_getbios_ni(radeon_info &info)
327 TRACE("card(%" B_PRId32 "): %s: called\n", info.id, __func__);
328 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
329 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
330 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
332 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
333 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);
336 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
338 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
341 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
344 write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
347 write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
351 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4);
353 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
355 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4);
359 uint32 romBase = info.pci->u.h0.rom_base;
360 uint32 romSize = info.pci->u.h0.rom_size;
367 result = mapAtomBIOS(info, romBase, romSize, true);
373 info.shared_info->rom_phys = romBase;
374 info.shared_info->rom_size = romSize;
379 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
382 write32(info.registers + R600_BUS_CNTL, bus_cntl);
383 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);
384 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);
385 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);
386 write32(info.registers + R600_ROM_CNTL, rom_cntl);
393 radeon_hd_getbios_r700(radeon_info &info)
395 TRACE("card(%" B_PRId32 "): %s: called\n", info.id, __func__);
396 uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL);
397 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
398 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
399 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
401 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
402 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);
405 write32(info.registers + RADEON_VIPH_CONTROL,
408 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
410 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
413 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
416 write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
419 write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
423 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4);
425 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
427 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4);
431 uint32 romBase = info.pci->u.h0.rom_base;
432 uint32 romSize = info.pci->u.h0.rom_size;
439 result = mapAtomBIOS(info, romBase, romSize);
445 info.shared_info->rom_phys = romBase;
446 info.shared_info->rom_size = romSize;
451 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
454 write32(info.registers + RADEON_VIPH_CONTROL, viph_control);
455 write32(info.registers + R600_BUS_CNTL, bus_cntl);
456 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);
457 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);
458 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);
459 write32(info.registers + R600_ROM_CNTL, rom_cntl);
466 radeon_hd_getbios_r600(radeon_info &info)
468 TRACE("card(%" B_PRId32 "): %s: called\n", info.id, __func__);
469 uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL);
470 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
471 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
472 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
474 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
475 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);
476 uint32 general_pwrmgt = read32(info.registers + R600_GENERAL_PWRMGT);
478 = read32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL);
480 = read32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL);
482 = read32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL);
484 = read32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL);
486 = read32(info.registers + R600_LOWER_GPIO_ENABLE);
489 write32(info.registers + RADEON_VIPH_CONTROL,
492 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
494 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
497 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
500 write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
503 write32(info.registers + R600_ROM_CNTL,
507 write32(info.registers + R600_GENERAL_PWRMGT,
509 write32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL,
511 write32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL,
513 write32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL,
515 write32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL,
517 write32(info.registers + R600_LOWER_GPIO_ENABLE,
522 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4);
524 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
526 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4);
530 uint32 romBase = info.pci->u.h0.rom_base;
531 uint32 romSize = info.pci->u.h0.rom_size;
538 result = mapAtomBIOS(info, romBase, romSize);
544 info.shared_info->rom_phys = romBase;
545 info.shared_info->rom_size = romSize;
550 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig);
553 write32(info.registers + RADEON_VIPH_CONTROL, viph_control);
554 write32(info.registers + R600_BUS_CNTL, bus_cntl);
555 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);
556 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);
557 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);
558 write32(info.registers + R600_ROM_CNTL, rom_cntl);
559 write32(info.registers + R600_GENERAL_PWRMGT, general_pwrmgt);
560 write32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL,
562 write32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL,
564 write32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL,
566 write32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL,
568 write32(info.registers + R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
575 radeon_hd_getbios_avivo(radeon_info &info)
577 TRACE("card(%" B_PRId32 "): %s: called\n", info.id, __func__);
578 uint32 sepromControl = read32(info.registers + RADEON_SEPROM_CNTL1);
579 uint32 viphControl = read32(info.registers + RADEON_VIPH_CONTROL);
580 uint32 busControl = read32(info.registers + RV370_BUS_CNTL);
581 uint32 d1vgaControl = read32(info.registers + AVIVO_D1VGA_CONTROL);
582 uint32 d2vgaControl = read32(info.registers + AVIVO_D2VGA_CONTROL);
584 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
585 uint32 gpioPadA = read32(info.registers + RADEON_GPIOPAD_A);
586 uint32 gpioPadEN = read32(info.registers + RADEON_GPIOPAD_EN);
587 uint32 gpioPadMask = read32(info.registers + RADEON_GPIOPAD_MASK);
589 write32(info.registers + RADEON_SEPROM_CNTL1,
592 write32(info.registers + RADEON_GPIOPAD_A, 0);
593 write32(info.registers + RADEON_GPIOPAD_EN, 0);
594 write32(info.registers + RADEON_GPIOPAD_MASK, 0);
597 write32(info.registers + RADEON_VIPH_CONTROL,
601 write32(info.registers + RV370_BUS_CNTL,
605 write32(info.registers + AVIVO_D1VGA_CONTROL,
608 write32(info.registers + AVIVO_D2VGA_CONTROL,
611 write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
614 uint32 romBase = info.pci->u.h0.rom_base;
615 uint32 romSize = info.pci->u.h0.rom_size;
622 result = mapAtomBIOS(info, romBase, romSize);
628 info.shared_info->rom_phys = romBase;
629 info.shared_info->rom_size = romSize;
633 write32(info.registers + RADEON_SEPROM_CNTL1, sepromControl);
634 write32(info.registers + RADEON_VIPH_CONTROL, viphControl);
635 write32(info.registers + RV370_BUS_CNTL, busControl);
636 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vgaControl);
637 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vgaControl);
638 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vgaRenderControl);
639 write32(info.registers + RADEON_GPIOPAD_A, gpioPadA);
640 write32(info.registers + RADEON_GPIOPAD_EN, gpioPadEN);
641 write32(info.registers + RADEON_GPIOPAD_MASK, gpioPadMask);
658 radeon_hd_init(radeon_info &info)
660 TRACE("card(%" B_PRId32 "): %s: called\n", info.id, __func__);
663 "Radeon %s 1002:%" B_PRIX32 "\n", __func__, info.id,
664 radeon_chip_name[info.chipsetID], info.pciID);
667 uint32 pciConfig = get_pci_config(info.pci, PCI_command, 2);
669 set_pci_config(info.pci, PCI_command, 2, pciConfig);
671 // *** Map shared info
673 info.shared_area = sharedCreator.Create("radeon hd shared info",
674 (void**)&info.shared_info, B_ANY_KERNEL_ADDRESS,
677 if (info.shared_area < B_OK) {
679 __func__, info.id);
680 return info.shared_area;
683 memset((void*)info.shared_info, 0, sizeof(radeon_shared_info));
687 const uint32 pciBarMmio = radeon_hd_pci_bar_mmio(info.chipsetID);
688 phys_addr_t addr = info.pci->u.h0.base_registers[pciBarMmio];
689 uint64 mmioSize = info.pci->u.h0.base_register_sizes[pciBarMmio];
691 && (info.pci->u.h0.base_register_flags[pciBarMmio] & PCI_address_type) == PCI_address_type_64) {
692 addr |= (uint64)info.pci->u.h0.base_registers[pciBarMmio + 1] << 32;
693 mmioSize |= (uint64)info.pci->u.h0.base_register_sizes[pciBarMmio + 1] << 32;
697 info.registers_area = mmioMapper.Map("radeon hd mmio", addr, mmioSize,
699 (void**)&info.registers);
702 __func__, info.id);
703 return info.registers_area;
708 if (info.chipsetID >= RADEON_TAHITI) {
710 info.shared_info->graphics_memory_size
711 = read32(info.registers + CONFIG_MEMSIZE_TAHITI) * 1024;
712 } else if (info.chipsetID >= RADEON_CEDAR) {
713 switch (info.chipsetID) {
716 info.shared_info->graphics_memory_size
717 = read32(info.registers + CONFIG_MEMSIZE) * 1024;
723 info.shared_info->graphics_memory_size
724 = read32(info.registers + CONFIG_MEMSIZE) / 1024;
727 } else if (info.chipsetID >= RADEON_R600) {
729 info.shared_info->graphics_memory_size
730 = read32(info.registers + CONFIG_MEMSIZE) / 1024;
734 if ((info.chipsetFlags & CHIP_IGP) != 0) {
736 uint32 tom = read32(info.registers + RADEON_NB_TOM);
737 info.shared_info->graphics_memory_size
739 write32(info.registers + RADEON_CONFIG_MEMSIZE,
740 info.shared_info->graphics_memory_size);
742 info.shared_info->graphics_memory_size
743 = read32(info.registers + RADEON_CONFIG_MEMSIZE);
744 if (info.shared_info->graphics_memory_size == 0) {
746 info.shared_info->graphics_memory_size = 8192;
747 write32(info.registers + RADEON_CONFIG_MEMSIZE,
748 info.shared_info->graphics_memory_size * 1024);
753 phys_addr_t fbAddr = info.pci->u.h0.base_registers[PCI_BAR_FB];
754 uint64 fbBarSize = info.pci->u.h0.base_register_sizes[PCI_BAR_FB];
755 if ((info.pci->u.h0.base_register_flags[PCI_BAR_FB] & PCI_address_type)
757 fbAddr |= (uint64)info.pci->u.h0.base_registers[PCI_BAR_FB + 1] << 32;
758 fbBarSize |= (uint64)info.pci->u.h0.base_register_sizes[PCI_BAR_FB + 1] << 32;
765 if (info.shared_info->graphics_memory_size == 0) {
769 info.shared_info->frame_buffer_size = fbBarSize;
770 } else if (info.shared_info->graphics_memory_size > fbBarSize) {
773 info.shared_info->frame_buffer_size = fbBarSize;
775 info.shared_info->frame_buffer_size
776 = info.shared_info->graphics_memory_size;
779 if (info.shared_info->frame_buffer_size < 8192) {
786 "MB video ram\n", __func__, info.shared_info->frame_buffer_size / 1024,
787 info.shared_info->graphics_memory_size / 1024);
793 info.framebuffer_area = frambufferMapper.Map("radeon hd frame buffer",
794 fbAddr, info.shared_info->frame_buffer_size * 1024,
796 (void**)&info.shared_info->frame_buffer);
800 __func__, info.id);
801 return info.framebuffer_area;
804 (addr_t)info.shared_info->frame_buffer);
806 (size_t)info.shared_info->frame_buffer_size * 1024);
809 vm_set_area_memory_type(info.framebuffer_area, fbAddr, B_MTR_WC);
813 info.shared_info->frame_buffer_area = info.framebuffer_area;
814 info.shared_info->frame_buffer_phys = fbAddr;
817 info.shared_info->deviceIndex = info.id;
818 info.shared_info->pciID = info.pciID;
819 info.shared_info->pciRev = info.pci->revision;
820 info.shared_info->chipsetID = info.chipsetID;
821 info.shared_info->chipsetFlags = info.chipsetFlags;
822 info.shared_info->dceMajor = info.dceMajor;
823 info.shared_info->dceMinor = info.dceMinor;
824 info.shared_info->registers_area = info.registers_area;
825 strlcpy(info.shared_info->deviceName,
826 info.deviceName, MAX_NAME_LENGTH);
827 strlcpy(info.shared_info->chipsetName,
828 radeon_chip_name[info.chipsetID], MAX_NAME_LENGTH);
832 status_t biosStatus = radeon_hd_getbios(info);
836 if (info.chipsetID >= RADEON_CAICOS)
837 biosStatus = radeon_hd_getbios_ni(info);
838 else if (info.chipsetID >= RADEON_RV770)
839 biosStatus = radeon_hd_getbios_r700(info);
840 else if (info.chipsetID >= RADEON_R600)
841 biosStatus = radeon_hd_getbios_r600(info);
842 else if (info.chipsetID >= RADEON_RS600)
843 biosStatus = radeon_hd_getbios_avivo(info);
861 if (mapAtomBIOS(info, romBase, romSize) == B_OK) {
864 info.shared_info->rom_phys = romBase;
865 info.shared_info->rom_size = romSize;
873 __func__, info.id);
876 __func__, info.id);
881 info.shared_info->has_rom = (biosStatus == B_OK) ? true : false;
882 info.shared_info->rom_area = (biosStatus == B_OK) ? info.rom_area : -1;
890 info.id, __func__);
891 info.shared_info->has_edid = true;
892 memcpy(&info.shared_info->edid_info, edidInfo, sizeof(edid1_info));
895 info.id, __func__);
896 info.shared_info->has_edid = false;
900 info.id, __func__);
903 info.id, radeon_thermal_query(info) / 1000);
910 radeon_hd_uninit(radeon_info &info)
912 TRACE("card(%" B_PRId32 "): %s called\n", info.id, __func__);
914 delete_area(info.shared_area);
915 delete_area(info.registers_area);
916 delete_area(info.framebuffer_area);
917 delete_area(info.rom_area);