Lines Matching refs:info
73 release_vblank_sem(intel_info &info)
76 if (get_sem_count(info.shared_info->vblank_sem, &count) == B_OK
78 release_sem_etc(info.shared_info->vblank_sem, -count,
88 gen8_enable_interrupts(intel_info& info, pipe_index pipe, bool enable)
91 ASSERT(info.device_type.Generation() >= 12 || pipe != INTEL_PIPE_D);
97 write32(info, regIdentity, ~0);
98 write32(info, regEnabled, value);
99 write32(info, regMask, ~value);
104 gen11_enable_global_interrupts(intel_info& info, bool enable)
106 write32(info, GEN11_GFX_MSTR_IRQ, enable ? GEN11_MASTER_IRQ : 0);
107 return enable ? 0 : read32(info, GEN11_GFX_MSTR_IRQ);
112 gen8_enable_global_interrupts(intel_info& info, bool enable)
114 write32(info, PCH_MASTER_INT_CTL_BDW, enable ? PCH_MASTER_INT_CTL_GLOBAL_BDW : 0);
115 return enable ? 0 : read32(info, PCH_MASTER_INT_CTL_BDW);
124 gen8_handle_interrupts(intel_info& info, uint32 interrupt)
129 uint32 identity = read32(info, regIdentity);
131 handled = release_vblank_sem(info);
132 write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW);
140 uint32 identity = read32(info, regIdentity);
142 handled = release_vblank_sem(info);
143 write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW);
151 uint32 identity = read32(info, regIdentity);
153 handled = release_vblank_sem(info);
154 write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW);
162 uint32 iir = read32(info, GEN8_DE_PORT_IIR);
164 write32(info, GEN8_DE_PORT_IIR, iir);
169 if (info.device_type.Generation() >= 11 && (interrupt & GEN11_DE_HPD_IRQ) != 0) {
171 uint32 iir = read32(info, GEN11_DE_HPD_IIR);
174 write32(info, GEN11_DE_HPD_IIR, iir);
181 uint32 iir = read32(info, SDEIIR);
184 write32(info, SDEIIR, iir);
185 if (info.shared_info->pch_info >= INTEL_PCH_ICP) {
186 uint32 ddiHotplug = read32(info, SHOTPLUG_CTL_DDI);
187 write32(info, SHOTPLUG_CTL_DDI, ddiHotplug);
190 uint32 tcHotplug = read32(info, SHOTPLUG_CTL_TC);
191 write32(info, SHOTPLUG_CTL_TC, tcHotplug);
211 * \param info Intel_extreme driver information
217 intel_get_interrupt_mask(intel_info& info, pipe_index pipe, bool enable)
220 bool hasPCH = info.pch_info != INTEL_PCH_NONE;
228 if (info.device_type.InGroup(INTEL_GROUP_SNB)
229 || info.device_type.InGroup(INTEL_GROUP_ILK))
238 if (info.device_type.InGroup(INTEL_GROUP_SNB)
239 || info.device_type.InGroup(INTEL_GROUP_ILK))
250 if (hasPCH && info.device_type.Generation() > 6)
257 if (enable && info.device_type.InFamily(INTEL_FAMILY_SER5))
265 intel_enable_interrupts(intel_info& info, pipes which, bool enable)
268 const uint32 pipeAMask = intel_get_interrupt_mask(info, INTEL_PIPE_A, true);
269 const uint32 pipeBMask = intel_get_interrupt_mask(info, INTEL_PIPE_B, true);
278 write32(info, find_reg(info, INTEL_INTERRUPT_IDENTITY), ~0);
281 write32(info, find_reg(info, INTEL_INTERRUPT_ENABLED), value);
282 write32(info, find_reg(info, INTEL_INTERRUPT_MASK), ~value);
287 intel_check_interrupt(intel_info& info, pipes& which)
290 const uint32 pipeAMask = intel_get_interrupt_mask(info, INTEL_PIPE_A, false);
291 const uint32 pipeBMask = intel_get_interrupt_mask(info, INTEL_PIPE_B, false);
292 const uint32 regIdentity = find_reg(info, INTEL_INTERRUPT_IDENTITY);
293 const uint32 interrupt = read32(info, regIdentity);
303 g35_clear_interrupt_status(intel_info& info, pipe_index pipe)
306 if (info.device_type.Generation() > 4)
312 write32(info, INTEL_DISPLAY_A_PIPE_STATUS, value);
315 write32(info, INTEL_DISPLAY_B_PIPE_STATUS, value);
324 intel_clear_pipe_interrupt(intel_info& info, pipe_index pipe)
328 g35_clear_interrupt_status(info, pipe);
330 const uint32 regIdentity = find_reg(info, INTEL_INTERRUPT_IDENTITY);
331 const uint32 bit = intel_get_interrupt_mask(info, pipe, false);
332 const uint32 identity = read32(info, regIdentity);
333 write32(info, regIdentity, identity | bit);
344 intel_info& info = *(intel_info*)data;
346 uint32 interrupt = gen8_enable_global_interrupts(info, false);
348 gen8_enable_global_interrupts(info, true);
352 int32 handled = gen8_handle_interrupts(info, interrupt);
354 gen8_enable_global_interrupts(info, true);
366 intel_info& info = *(intel_info*)data;
368 uint32 interrupt = gen11_enable_global_interrupts(info, false);
371 gen11_enable_global_interrupts(info, true);
377 handled = gen8_handle_interrupts(info, read32(info, GEN11_DISPLAY_INT_CTL));
379 gen11_enable_global_interrupts(info, true);
387 intel_info &info = *(intel_info*)data;
390 bool shouldHandle = intel_check_interrupt(info, which);
399 handled = release_vblank_sem(info);
401 intel_clear_pipe_interrupt(info, INTEL_PIPE_A);
405 handled = release_vblank_sem(info);
407 intel_clear_pipe_interrupt(info, INTEL_PIPE_B);
413 handled = release_vblank_sem(info);
415 intel_clear_pipe_interrupt(info, INTEL_PIPE_C);
419 shouldHandle = intel_check_interrupt(info, which);
427 init_interrupt_handler(intel_info &info)
429 info.shared_info->vblank_sem = create_sem(0, "intel extreme vblank");
430 if (info.shared_info->vblank_sem < B_OK)
440 || set_sem_owner(info.shared_info->vblank_sem, threadInfo.team)
446 info.irq = 0;
447 info.use_msi = false;
448 if (info.pci->u.h0.interrupt_pin != 0x00) {
449 info.irq = info.pci->u.h0.interrupt_line;
450 if (info.irq == 0xff)
451 info.irq = 0;
453 if (gPCI->get_msi_count(info.pci->bus,
454 info.pci->device, info.pci->function) >= 1) {
456 if (gPCI->configure_msi(info.pci->bus, info.pci->device,
457 info.pci->function, 1, &msiVector) == B_OK
458 && gPCI->enable_msi(info.pci->bus, info.pci->device,
459 info.pci->function) == B_OK) {
461 info.irq = msiVector;
462 info.use_msi = true;
466 if (status == B_OK && info.irq != 0) {
469 info.fake_interrupts = false;
471 if (info.device_type.Generation() >= 8) {
473 if (info.device_type.Generation() >= 11)
475 status = install_io_interrupt_handler(info.irq,
476 handler, (void*)&info, 0);
478 gen8_enable_interrupts(info, INTEL_PIPE_A, true);
479 gen8_enable_interrupts(info, INTEL_PIPE_B, true);
480 if (info.device_type.Generation() >= 11)
481 gen8_enable_interrupts(info, INTEL_PIPE_C, true);
482 gen8_enable_global_interrupts(info, true);
484 if (info.device_type.Generation() >= 11) {
485 if (info.shared_info->pch_info >= INTEL_PCH_ICP) {
486 read32(info, SDEIIR);
487 write32(info, SDEIER, 0xffffffff);
488 write32(info, SDEIMR, ~SDE_GMBUS_ICP);
489 read32(info, SDEIMR);
496 read32(info, GEN8_DE_PORT_IIR);
497 write32(info, GEN8_DE_PORT_IER, mask);
498 write32(info, GEN8_DE_PORT_IMR, ~mask);
499 read32(info, GEN8_DE_PORT_IMR);
501 read32(info, GEN8_DE_MISC_IIR);
502 write32(info, GEN8_DE_MISC_IER, GEN8_DE_EDP_PSR);
503 write32(info, GEN8_DE_MISC_IMR, ~GEN8_DE_EDP_PSR);
504 read32(info, GEN8_DE_MISC_IMR);
506 read32(info, GEN11_GU_MISC_IIR);
507 write32(info, GEN11_GU_MISC_IER, GEN11_GU_MISC_GSE);
508 write32(info, GEN11_GU_MISC_IMR, ~GEN11_GU_MISC_GSE);
509 read32(info, GEN11_GU_MISC_IMR);
511 read32(info, GEN11_DE_HPD_IIR);
512 write32(info, GEN11_DE_HPD_IER,
514 write32(info, GEN11_DE_HPD_IMR, 0xffffffff);
515 read32(info, GEN11_DE_HPD_IMR);
517 write32(info, GEN11_TC_HOTPLUG_CTL, 0);
518 write32(info, GEN11_TBT_HOTPLUG_CTL, 0);
520 if (info.shared_info->pch_info >= INTEL_PCH_ICP) {
521 if (info.shared_info->pch_info <= INTEL_PCH_TGP)
522 write32(info, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
523 read32(info, SDEIMR);
524 write32(info, SDEIMR, 0x3f023f07);
525 read32(info, SDEIMR);
527 uint32 ctl = read32(info, SHOTPLUG_CTL_DDI);
533 write32(info, SHOTPLUG_CTL_DDI, ctl);
534 ctl = read32(info, SHOTPLUG_CTL_TC);
542 write32(info, SHOTPLUG_CTL_TC, ctl);
545 gen11_enable_global_interrupts(info, true);
549 status = install_io_interrupt_handler(info.irq,
550 &intel_interrupt_handler, (void*)&info, 0);
552 g35_clear_interrupt_status(info, INTEL_PIPE_A);
553 g35_clear_interrupt_status(info, INTEL_PIPE_B);
558 intel_enable_interrupts(info, which, true);
566 info.fake_interrupts = true;
574 delete_sem(info.shared_info->vblank_sem);
575 info.shared_info->vblank_sem = B_ERROR;
584 intel_free_memory(intel_info &info, addr_t base)
586 return gGART->free_memory(info.aperture, base);
591 intel_allocate_memory(intel_info &info, size_t size, size_t alignment,
594 return gGART->allocate_memory(info.aperture, size, alignment,
600 intel_extreme_init(intel_info &info)
603 info.aperture = gGART->map_aperture(info.pci->bus, info.pci->device,
604 info.pci->function, 0, &info.aperture_base);
605 if (info.aperture < B_OK) {
607 strerror(info.aperture));
608 return info.aperture;
612 info.shared_area = sharedCreator.Create("intel extreme shared info",
613 (void**)&info.shared_info, B_ANY_KERNEL_ADDRESS,
617 if (info.shared_area < B_OK) {
619 gGART->unmap_aperture(info.aperture);
620 return info.shared_area;
624 gPCI->set_powerstate(info.pci->bus, info.pci->device, info.pci->function,
627 memset((void*)info.shared_info, 0, sizeof(intel_shared_info));
630 if (info.device_type.Generation() >= 3) {
646 phys_addr_t addr = info.pci->u.h0.base_registers[mmioIndex];
647 uint64 barSize = info.pci->u.h0.base_register_sizes[mmioIndex];
648 if ((info.pci->u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) {
649 addr |= (uint64)info.pci->u.h0.base_registers[mmioIndex + 1] << 32;
650 barSize |= (uint64)info.pci->u.h0.base_register_sizes[mmioIndex + 1] << 32;
653 info.registers_area = mmioMapper.Map("intel extreme mmio", addr, barSize,
656 (void**)&info.registers);
659 gGART->unmap_aperture(info.aperture);
660 return info.registers_area;
663 bool hasPCH = (info.pch_info != INTEL_PCH_NONE);
666 info.device_type.Generation(), hasPCH ? "with" : "without");
668 uint32* blocks = info.shared_info->register_blocks;
699 if (info.device_type.InGroup(INTEL_GROUP_VLV)) {
717 set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci,
725 ring_buffer &primary = info.shared_info->primary_ring_buffer;
726 if (intel_allocate_memory(info, 16 * B_PAGE_SIZE, 0, 0,
730 primary.offset = (addr_t)primary.base - info.aperture_base;
734 intel_en_gating(info);
737 intel_en_downclock(info);
744 gGART->get_aperture_info(info.aperture, &apertureInfo);
746 info.shared_info->registers_area = info.registers_area;
747 info.shared_info->graphics_memory = (uint8*)info.aperture_base;
748 info.shared_info->physical_graphics_memory = apertureInfo.physical_base;
749 info.shared_info->graphics_memory_size = apertureInfo.size;
750 info.shared_info->frame_buffer = 0;
751 info.shared_info->dpms_mode = B_DPMS_ON;
752 info.shared_info->min_brightness = 2;
753 info.shared_info->internal_crt_support = true;
754 info.shared_info->pch_info = info.pch_info;
755 info.shared_info->device_type = info.device_type;
757 // Pull VBIOS info for later use
758 info.shared_info->got_vbt = parse_vbt_from_bios(info.shared_info);
761 if (info.device_type.InFamily(INTEL_FAMILY_8xx))
762 info.shared_info->single_head_locked = 1;
764 if (info.device_type.InFamily(INTEL_FAMILY_SER5)) {
765 info.shared_info->pll_info.reference_frequency = 120000;// 120 MHz
766 info.shared_info->pll_info.max_frequency = 350000;
768 info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
769 } else if (info.device_type.InFamily(INTEL_FAMILY_9xx)) {
770 info.shared_info->pll_info.reference_frequency = 96000; // 96 MHz
771 info.shared_info->pll_info.max_frequency = 400000;
773 info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
774 } else if (info.device_type.HasDDI() && (info.device_type.Generation() <= 8)) {
775 info.shared_info->pll_info.reference_frequency = 135000;// 135 MHz
776 info.shared_info->pll_info.max_frequency = 350000;
778 info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
779 } else if ((info.device_type.Generation() >= 9) &&
780 info.device_type.InGroup(INTEL_GROUP_SKY)) {
781 info.shared_info->pll_info.reference_frequency = 24000; // 24 MHz
782 info.shared_info->pll_info.max_frequency = 350000;
784 info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
785 } else if (info.device_type.Generation() >= 9) {
787 (read32(info, ICL_DSSM) & ICL_DSSM_REF_FREQ_MASK) >> ICL_DSSM_REF_FREQ_SHIFT;
790 info.shared_info->pll_info.reference_frequency = 24000; // 24 MHz
793 info.shared_info->pll_info.reference_frequency = 19200; // 19.2 MHz
796 info.shared_info->pll_info.reference_frequency = 38400; // 38.4 MHz
800 info.shared_info->pll_info.reference_frequency = 24000; // 24 MHz
803 info.shared_info->pll_info.max_frequency = 350000;
805 info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
807 info.shared_info->pll_info.reference_frequency = 48000; // 48 MHz
808 info.shared_info->pll_info.max_frequency = 350000;
810 info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
813 info.shared_info->pll_info.divisor_register = INTEL_DISPLAY_A_PLL_DIVISOR_0;
816 strlcpy(info.shared_info->device_identifier, info.device_identifier,
817 sizeof(info.shared_info->device_identifier));
819 strcpy(info.shared_info->device_identifier, info.device_identifier);
824 status_t status = intel_allocate_memory(info, B_PAGE_SIZE, 0,
825 intel_uses_physical_overlay(*info.shared_info)
827 (addr_t*)&info.overlay_registers,
828 &info.shared_info->physical_overlay_registers);
830 info.shared_info->overlay_offset = (addr_t)info.overlay_registers
831 - info.aperture_base;
834 info.shared_info->overlay_offset, info.overlay_registers,
835 info.aperture_base, info.shared_info->physical_overlay_registers);
836 init_overlay_registers(info.overlay_registers);
845 if (intel_allocate_memory(info, B_PAGE_SIZE, 0, B_APERTURE_NEED_PHYSICAL,
846 (addr_t*)info.shared_info->status_page,
847 &info.shared_info->physical_status_page) == B_OK) {
851 intel_allocate_memory(info, B_PAGE_SIZE, 0, B_APERTURE_NEED_PHYSICAL,
852 (addr_t*)&info.shared_info->cursor_memory,
853 &info.shared_info->physical_cursor_memory);
859 info.shared_info->has_vesa_edid_info = true;
860 memcpy(&info.shared_info->vesa_edid_info, edidInfo, sizeof(edid1_info));
863 init_interrupt_handler(info);
866 if (info.device_type.Generation() == 5) {
867 info.shared_info->fdi_link_frequency = (read32(info, FDI_PLL_BIOS_0)
869 info.shared_info->fdi_link_frequency *= 100;
871 info.shared_info->fdi_link_frequency = 2700;
873 if (info.shared_info->pch_info >= INTEL_PCH_CNP) {
874 // TODO read/write info.shared_info->hraw_clock
876 info.shared_info->hraw_clock = (read32(info, PCH_RAWCLK_FREQ)
878 TRACE("%s: rawclk rate: %" B_PRIu32 " kHz\n", __func__, info.shared_info->hraw_clock);
881 // TODO read info.shared_info->hraw_clock
882 info.shared_info->fdi_link_frequency = 0;
885 if (info.device_type.InGroup(INTEL_GROUP_BDW)) {
886 uint32 lcpll = read32(info, LCPLL_CTL);
888 info.shared_info->hw_cdclk = 800000;
889 else if ((read32(info, FUSE_STRAP) & HSW_CDCLK_LIMIT) != 0)
890 info.shared_info->hw_cdclk = 450000;
892 info.shared_info->hw_cdclk = 450000;
894 info.shared_info->hw_cdclk = 540000;
896 info.shared_info->hw_cdclk = 337500;
898 info.shared_info->hw_cdclk = 675000;
899 } else if (info.device_type.InGroup(INTEL_GROUP_HAS)) {
900 uint32 lcpll = read32(info, LCPLL_CTL);
902 info.shared_info->hw_cdclk = 800000;
903 else if ((read32(info, FUSE_STRAP) & HSW_CDCLK_LIMIT) != 0)
904 info.shared_info->hw_cdclk = 450000;
906 info.shared_info->hw_cdclk = 450000;
909 info.shared_info->hw_cdclk = 337500;
912 info.shared_info->hw_cdclk = 540000;
913 } else if (info.device_type.InGroup(INTEL_GROUP_SNB)
914 || info.device_type.InGroup(INTEL_GROUP_IVB)) {
915 info.shared_info->hw_cdclk = 400000;
916 } else if (info.device_type.InGroup(INTEL_GROUP_ILK)) {
917 info.shared_info->hw_cdclk = 450000;
919 TRACE("%s: hw_cdclk: %" B_PRIu32 " kHz\n", __func__, info.shared_info->hw_cdclk);
927 intel_extreme_uninit(intel_info &info)
931 if (!info.fake_interrupts && info.shared_info->vblank_sem > 0) {
933 if (info.device_type.Generation() >= 8) {
934 if (info.device_type.Generation() >= 11) {
935 gen11_enable_global_interrupts(info, false);
937 gen8_enable_global_interrupts(info, false);
939 if (info.device_type.Generation() >= 11)
941 remove_io_interrupt_handler(info.irq, handler, &info);
943 write32(info, find_reg(info, INTEL_INTERRUPT_ENABLED), 0);
944 write32(info, find_reg(info, INTEL_INTERRUPT_MASK), ~0);
945 remove_io_interrupt_handler(info.irq, intel_interrupt_handler, &info);
948 if (info.use_msi) {
949 gPCI->disable_msi(info.pci->bus,
950 info.pci->device, info.pci->function);
951 gPCI->unconfigure_msi(info.pci->bus,
952 info.pci->device, info.pci->function);
956 gGART->unmap_aperture(info.aperture);
958 delete_area(info.registers_area);
959 delete_area(info.shared_area);