Lines Matching refs:port
122 pcm_dev * port,
126 state->control = get_direct(port->card, 0);
127 state->imask = get_direct(port->card, 1);
130 state->regs[ix] = get_indirect(port->card, ix+0x30);
138 pcm_dev * port,
142 set_direct(port->card, 0, state->control, 0xff);
145 set_indirect(port->card, ix, state->regs[ix]+0x30, 0xff);
148 set_direct(port->card, 1, state->imask, 0xff);
154 pcm_dev * port)
156 set_direct(port->card, 0x1b, 0x40, 0x40);
158 set_direct(port->card, 0x1b, 0x00, 0x40);
166 pcm_dev * port)
168 set_direct(port->card, 0x24, 0x40, 0x40); // mute wave stream
169 set_direct(port->card, 0x02, 0, 0x03); // stop both ch0 and ch1
171 set_direct(port->card, 0x02, 0x0c, 0x0c); // reset both ch0 and ch1
172 set_direct(port->card, 0x02, 0, 0x0c);
179 pcm_dev * port)
187 if (port->config.format == 0x11) {
188 memset((void*)port->card->low_mem, 0x80, port->config.play_buf_size +
189 port->config.rec_buf_size);
192 memset((void *)port->card->low_mem, 0, port->config.play_buf_size +
193 port->config.rec_buf_size);
196 port->wr_cur = port->wr_2;
197 port->wr_silence = port->config.play_buf_size;
198 port->was_written = 0;
199 port->rd_cur = port->rd_2;
200 port->was_read = port->config.rec_buf_size/2; /* how much has been read */
201 port->wr_total = 0;
202 port->rd_total = 0;
215 port->config.play_buf_size/2, port->config.rec_buf_size/2));
217 PCI_IO_WR(port->dma_c, ((uint32)port->card->low_phys+
218 port->config.play_buf_size)&0xff);
219 PCI_IO_WR(port->dma_c+1, (((uint32)port->card->low_phys+
220 port->config.play_buf_size)>>8)&0xff);
221 PCI_IO_WR(port->dma_c+2, (((uint32)port->card->low_phys+
222 port->config.play_buf_size)>>16)&0xff);
223 PCI_IO_WR(port->dma_c+3, 0);
225 if (port->config.format != 0x11)
228 if (port->config.channels == 2)
230 PCI_IO_WR(port->dma_c+4, (port->config.rec_buf_size/sample_size-1)&0xff);
231 PCI_IO_WR(port->dma_c+5, ((port->config.rec_buf_size/sample_size-1)>>8)&0xff);
232 PCI_IO_WR(port->dma_c+6, (port->rd_size/sample_size-1)&0xff);
233 PCI_IO_WR(port->dma_c+7, ((port->rd_size/sample_size-1)>>8)&0xff);
235 PCI_IO_WR(port->dma_a, ((uint32)port->card->low_phys)&0xff);
236 PCI_IO_WR(port->dma_a+1, ((uint32)port->card->low_phys>>8)&0xff);
237 PCI_IO_WR(port->dma_a+2, ((uint32)port->card->low_phys>>16)&0xff);
238 PCI_IO_WR(port->dma_a+3, 0);
239 PCI_IO_WR(port->dma_a+4, (port->config.play_buf_size/sample_size-1)&0xff);
240 PCI_IO_WR(port->dma_a+5, ((port->config.play_buf_size/sample_size-1)>>8)&0xff);
241 PCI_IO_WR(port->dma_a+6, (port->wr_size/sample_size-1)&0xff);
242 PCI_IO_WR(port->dma_a+7, ((port->wr_size/sample_size-1)>>8)&0xff);
246 ddprintf(("cmedia_pci: DMA starts as %lx/%lx\n", port->config.format, port->open_mode));
247 set_direct(port->card, 0x24, 0x00, 0x40);
250 set_direct(port->card, 0, 0x02, 0x03);
251 set_direct(port->card, 0x02, 0x03, 0x03);
260 pcm_dev * port,
317 if (!force && abs(config->sample_rate - port->config.sample_rate) < config->sample_rate/250) {
390 stop_dma(port);
395 port->config.sample_rate = config->sample_rate;
396 set_direct(port->card, 0x05, (asr<<5)|(asr<<2), 0xfc);
399 port->config.sample_rate = ((float)m+2.0)*(F_REF/1000.0)/
401 config->sample_rate = port->config.sample_rate;
405 set_indirect(port->card, 0x24, m, 0xff);
406 set_indirect(port->card, 0x25, (r<<5)|n, 0xff);
407 set_indirect(port->card, 0x22, 0x00, 0xff);
411 if (force || config->channels != port->config.channels ||
412 config->format != port->config.format) {
420 set_direct(port->card, 0x08, (val<<2)|val, 0x0f); /* MCE -- may take time to take effect */
421 port->config.channels = config->channels;
422 port->config.format = config->format;
424 if (force || config->big_endian != port->config.big_endian) {
425 port->config.big_endian = config->big_endian;
427 if (force || config->buf_header != port->config.buf_header) {
428 port->config.buf_header = config->buf_header;
430 if (force || config->play_buf_size != port->config.play_buf_size*2) {
431 port->config.play_buf_size = config->play_buf_size*2; /* because we break it in two */
433 if (force || config->rec_buf_size != port->config.rec_buf_size*2) {
434 port->config.rec_buf_size = config->rec_buf_size*2; /* because we break it in two */
439 ddprintf(("cmedia_pci: play %04lx rec %04lx\n", port->config.play_buf_size/2,
440 port->config.rec_buf_size/2));
442 port->wr_1 = port->card->low_mem;
443 port->wr_2 = port->wr_1+port->config.play_buf_size/2;
444 port->wr_size = port->config.play_buf_size/2;
446 port->rd_1 = port->card->low_mem+port->config.play_buf_size;
447 port->rd_2 = port->rd_1+port->config.rec_buf_size/2;
448 port->rd_size = port->config.rec_buf_size/2;
452 start_dma(port);
465 pcm_dev * port = NULL;
486 *cookie = port = &cards[ix].pcm;
488 acquire_sem(port->init_sem);
490 prev_mode = port->open_mode;
492 atomic_or(&port->open_mode, kRecord);
495 atomic_or(&port->open_mode, kPlayback);
498 atomic_or(&port->open_mode, kPlayback|kRecord);
501 if (atomic_add(&port->open_count, 1) == 0) {
505 port->card = &cards[ix];
506 port->config = default_pcm;
507 port->config.play_buf_size *= 2;
508 port->config.rec_buf_size *= 2;
511 B_INITIALIZE_SPINLOCK(&port->wr_lock);
512 port->dma_a = cards[ix].dma_base;
513 port->wr_1 = cards[ix].low_mem;
514 port->wr_2 = cards[ix].low_mem+port->config.play_buf_size/2;
515 port->wr_size = port->config.play_buf_size/2;
516 port->write_waiting = 0;
517 sprintf(name_buf, "WS:%s", port->name);
519 port->write_sem = create_sem(0, name_buf);
520 if (port->write_sem < B_OK) {
521 port->open_count = 0;
522 return port->write_sem;
524 set_sem_owner(port->write_sem, B_SYSTEM_TEAM);
526 port->wr_entry = create_sem(1, name_buf);
527 if (port->wr_entry < B_OK) {
528 delete_sem(port->write_sem);
529 port->open_count = 0;
530 return port->wr_entry;
532 set_sem_owner(port->wr_entry, B_SYSTEM_TEAM);
534 port->wr_time_wait = 0;
535 port->wr_time_sem = create_sem(0, name_buf);
536 if (port->wr_time_sem < B_OK) {
537 delete_sem(port->write_sem);
538 delete_sem(port->wr_entry);
539 port->open_count = 0;
540 return port->wr_time_sem;
542 set_sem_owner(port->wr_time_sem, B_SYSTEM_TEAM);
546 B_INITIALIZE_SPINLOCK(&port->rd_lock);
547 port->dma_c = cards[ix].dma_base+0x08;
548 port->rd_1 = cards[ix].low_mem+port->config.play_buf_size;
549 port->rd_2 = cards[ix].low_mem+port->config.play_buf_size+port->config.rec_buf_size/2;
550 port->rd_size = port->config.rec_buf_size/2;
551 port->read_waiting = 0;
553 port->read_sem = create_sem(0, name_buf);
554 if (port->read_sem < B_OK) {
555 delete_sem(port->write_sem);
556 delete_sem(port->wr_entry);
557 delete_sem(port->wr_time_sem);
558 port->open_count = 0;
559 return port->read_sem;
561 set_sem_owner(port->read_sem, B_SYSTEM_TEAM);
563 port->rd_entry = create_sem(1, name_buf);
564 if (port->rd_entry < B_OK) {
565 delete_sem(port->write_sem);
566 delete_sem(port->wr_entry);
567 delete_sem(port->read_sem);
568 delete_sem(port->wr_time_sem);
569 port->open_count = 0;
570 return port->rd_entry;
572 set_sem_owner(port->rd_entry, B_SYSTEM_TEAM);
574 port->rd_time_wait = 0;
575 port->rd_time_sem = create_sem(0, name_buf);
576 if (port->rd_time_sem < B_OK) {
577 delete_sem(port->write_sem);
578 delete_sem(port->wr_entry);
579 delete_sem(port->read_sem);
580 delete_sem(port->wr_time_sem);
581 delete_sem(port->rd_entry);
582 port->open_count = 0;
583 return port->rd_time_sem;
585 set_sem_owner(port->rd_time_sem, B_SYSTEM_TEAM);
587 port->rd_time = 0;
588 port->next_rd_time = 0;
589 port->wr_time = 0;
593 port->old_cap_sem = -1;
594 port->old_play_sem = -1;
598 configure_pcm(port, &default_pcm, true);
602 increment_interrupt_handler(port->card);
604 set_direct(port->card, 0x0e, 0x03, 0x03); /* */
605 start_dma(port);
609 if (prev_mode != port->open_mode) {
610 pcm_cfg temp = port->config;
613 configure_pcm(port, &temp, false); /* change rec/play if needed */
616 release_sem(port->init_sem);
630 pcm_dev * port = (pcm_dev *)cookie;
636 acquire_sem(port->init_sem);
638 if (atomic_add(&port->open_count, -1) == 1) {
642 acquire_spinlock(&port->card->hardware);
645 stop_dma(port);
646 set_direct(port->card, 0x0e, 0x00, 0x03); /* */
648 if (port->config.format == 0x11) {
649 memset((void *)port->wr_1, 0x80, port->config.play_buf_size); /* play silence */
652 memset((void *)port->wr_1, 0, port->config.play_buf_size); /* play silence */
656 release_spinlock(&port->card->hardware);
659 delete_sem(port->write_sem);
660 delete_sem(port->read_sem);
661 delete_sem(port->wr_entry);
662 delete_sem(port->rd_entry);
663 delete_sem(port->rd_time_sem);
664 delete_sem(port->wr_time_sem);
665 port->write_sem = -1;
666 port->read_sem = -1;
667 port->wr_entry = -1;
668 port->rd_entry = -1;
669 port->rd_time_sem = -1;
670 port->wr_time_sem = -1;
672 release_sem(port->init_sem);
676 snooze(port->config.play_buf_size*1000/(port->config.sample_rate*
677 (port->config.format&0xf)*port->config.channels/1000));
688 pcm_dev * port = (pcm_dev *)cookie;
692 acquire_sem(port->init_sem);
700 acquire_spinlock(&port->card->hardware);
702 decrement_interrupt_handler(port->card);
704 release_spinlock(&port->card->hardware);
707 release_sem(port->init_sem);
724 pcm_dev * port = (pcm_dev *)cookie;
726 pcm_cfg config = port->config;
736 memcpy(data, &config, sizeof(port->config));
749 atomic_add(&port->rd_time_wait, 1);
750 err = acquire_sem(port->rd_time_sem);
755 acquire_spinlock(&port->rd_lock);
756 ((sv_timing *)data)->time = port->rd_time;
757 ((sv_timing *)data)->bytes = port->rd_total;
758 ((sv_timing *)data)->skipped = port->rd_skipped;
760 release_spinlock(&port->rd_lock);
765 atomic_add(&port->wr_time_wait, 1);
766 err = acquire_sem(port->wr_time_sem);
771 acquire_spinlock(&port->wr_lock);
772 ((sv_timing *)data)->time = port->wr_time;
773 ((sv_timing *)data)->bytes = port->wr_total;
774 ((sv_timing *)data)->skipped = port->wr_skipped;
776 release_spinlock(&port->wr_lock);
784 acquire_spinlock(&port->wr_lock);
785 acquire_spinlock(&port->rd_lock);
786 ((sv_handshake *)data)->wr_time = port->wr_time;
787 ((sv_handshake *)data)->wr_skipped = port->wr_skipped;
788 ((sv_handshake *)data)->rd_time = port->rd_time;
789 ((sv_handshake *)data)->rd_skipped = port->rd_skipped;
790 ((sv_handshake *)data)->wr_total = port->wr_total;
791 ((sv_handshake *)data)->rd_total = port->rd_total;
794 release_spinlock(&port->rd_lock);
795 release_spinlock(&port->wr_lock);
804 acquire_spinlock(&port->card->hardware);
808 if (!port->config.big_endian == !B_HOST_IS_BENDIAN) {
822 u = get_indirect(port->card, 0x30)>>2;
827 u = get_indirect(port->card, 0x3d); // Legacy SB compatible Mixer
846 u = get_indirect(port->card, 0x3f)>>4;
849 u = get_direct(port->card, 0x25)<<4;
852 u = get_indirect(port->card, 0x36)>>3;
855 u = get_indirect(port->card, 0x3c)<<5;
858 u = get_indirect(port->card, 0x34)>>3;
861 u = get_direct(port->card, 0x24);
864 u = get_indirect(port->card, 0x38)>>3;
867 u = get_indirect(port->card, 0x3c)<<3;
870 u = get_indirect(port->card, 0x32)>>2;
873 u = get_direct(port->card, 0x24)<<1;
877 u = get_indirect(port->card, 0x3e);
896 u = get_indirect(port->card, 0x40)>>4;
899 u = get_indirect(port->card, 0x37)>>3;
901 u = get_indirect(port->card, 0x3c)<<6;
903 u = get_indirect(port->card, 0x35)>>3;
905 u = get_direct(port->card, 0x24);
907 u = get_indirect(port->card, 0x39)>>3;
909 u = get_indirect(port->card, 0x3c)<<4;
911 u = get_indirect(port->card, 0x33)>>2;
913 u = get_direct(port->card, 0x24)<<1;
916 release_spinlock(&port->card->hardware);
925 acquire_spinlock(&port->card->hardware);
968 set_indirect(port->card, 0x30, u<<3, 0xff);
969 set_indirect(port->card, 0x31, u<<3, 0xff);
987 set_indirect(port->card, 0x3d, u, 0xff);
989 set_indirect(port->card, 0x3f, u<<4, 0xff);
991 set_direct(port->card, 0x25, u, 0x01);
994 set_indirect(port->card, 0x36, u<<3, 0xff);
996 set_indirect(port->card, 0x3c, u, 0x04);
999 set_indirect(port->card, 0x34, u<<3, 0xff);
1001 set_direct(port->card, 0x24, u, 0x80);
1004 set_indirect(port->card, 0x38, u<<3, 0xff);
1006 set_indirect(port->card, 0x3c, u, 0x10);
1009 set_indirect(port->card, 0x32, u<<2, 0xff);
1011 set_direct(port->card, 0x24, u, 0x40);
1028 set_indirect(port->card, 0x3e, u, 0xff);
1030 set_indirect(port->card, 0x40, u<<4, 0xff);
1032 set_direct(port->card, 0x25, u, 0x01);
1034 set_indirect(port->card, 0x37, u<<3, 0xff);
1036 set_indirect(port->card, 0x3c, u, 0x02);
1038 set_indirect(port->card, 0x35, u<<3, 0xff);
1040 set_direct(port->card, 0x24, u, 0x80);
1042 set_indirect(port->card, 0x39, u<<3, 0xff);
1044 set_indirect(port->card, 0x3c, u, 0x08);
1046 set_indirect(port->card, 0x33, u<<2, 0xff);
1048 set_direct(port->card, 0x24, u, 0x40);
1050 release_spinlock(&port->card->hardware);
1054 port->old_play_sem = *(sem_id *)data;
1058 port->old_cap_sem = *(sem_id *)data;
1073 buf->time = port->wr_time;
1074 buf->sample_clock = port->wr_total/4 * 10000 / 441;
1075 err = release_sem(port->old_play_sem);
1081 buf->time = port->rd_time;
1082 buf->sample_clock = port->rd_total/4 * 10000 / 441;
1083 err = release_sem(port->old_cap_sem);
1111 reg_value = get_direct( port->card, 0x04 );
1118 set_direct( port->card, 0x04, 0x00, 0x80 );
1120 set_direct( port->card, 0x04, 0x80, 0x80 );
1129 reg_value = get_direct( port->card, 0x16 ); // Adresse 0x16
1136 set_direct( port->card, 0x16, 0x00, 0x80);
1138 set_direct( port->card, 0x16, 0x80, 0x80 );
1146 reg_value = get_direct( port->card, 0x24 );
1154 set_direct( port->card, 0x24, 0x00, 0x01 );
1156 set_direct( port->card, 0x24, 0x01, 0x01 );
1162 reg_value = get_direct( port->card, 0x1b );
1169 set_direct( port->card, 0x1b, 0x00, 0x02 );
1171 set_direct( port->card, 0x1b, 0x02, 0x02 );
1176 reg_value = get_direct( port->card, 0x08 ); // Adresse 0x08
1184 set_direct( port->card, 0x08, 0x00, 0x80 );
1186 set_direct( port->card, 0x08, 0x80, 0x80 ); // Adresse 0x08, Daten 0x80
1193 reg_value = get_direct( port->card, 0x16 );
1200 set_direct( port->card, 0x16, 0x00, 0x40 );
1202 set_direct( port->card, 0x16, 0x40, 0x40 );
1208 reg_value = get_direct( port->card, 0x27 );
1215 set_direct( port->card, 0x27, 0x00, 0x02 );
1217 set_direct( port->card, 0x27, 0x02, 0x02 );
1224 reg_value = get_direct( port->card, 0x1b );
1235 set_direct( port->card, 0x1b, 0x00, 0x04 );
1237 set_direct( port->card, 0x1b, 0x04, 0x04 );
1271 acquire_spinlock(&port->card->hardware);
1272 err = configure_pcm(port, &config, false);
1273 release_spinlock(&port->card->hardware);
1351 pcm_dev * port = (pcm_dev *)cookie;
1358 int hdrsize = port->config.buf_header;
1367 err = acquire_sem_etc(port->rd_entry, 1, B_CAN_INTERRUPT, 0);
1372 hdr.capture_time = port->rd_time;
1378 atomic_add(&port->read_waiting, 1);
1379 err = acquire_sem_etc(port->read_sem, 1, B_CAN_INTERRUPT, 0);
1381 release_sem(port->rd_entry);
1388 acquire_spinlock(&port->rd_lock);
1390 block = port->rd_size-port->was_read;
1392 if (port->config.format == 0x24) {
1400 switch (port->config.format) {
1402 copy_short_to_float((float *)data, (const short *)(port->rd_cur+port->was_read),
1403 block, !B_HOST_IS_LENDIAN == !port->config.big_endian);
1407 if (!B_HOST_IS_LENDIAN == !port->config.big_endian) {
1409 swap_copy((short *)data, (const short *)(port->rd_cur+port->was_read), block);
1416 memcpy(data, (void *)(port->rd_cur+port->was_read), block);
1420 port->was_read += block;
1422 release_spinlock(&port->rd_lock);
1435 hdr.sample_rate = port->config.sample_rate;
1442 release_sem(port->rd_entry);
1455 pcm_dev * port = (pcm_dev *)cookie;
1467 err = acquire_sem_etc(port->wr_entry, 1, B_CAN_INTERRUPT, 0);
1472 atomic_add(&port->write_waiting, 1);
1473 if (port->config.format == 0x24) {
1480 err = acquire_sem_etc(port->write_sem, 1, B_CAN_INTERRUPT, 0);
1482 release_sem(port->wr_entry);
1507 acquire_spinlock(&port->wr_lock);
1509 block = port->wr_size-port->was_written;
1512 if (atomic_add(&port->write_waiting, -1) > 0) {
1513 release_sem_etc(port->write_sem, 1, B_DO_NOT_RESCHEDULE);
1516 atomic_add(&port->write_waiting, 1); /* undo damage */
1521 atomic_add(&port->write_waiting, 1); /* we will loop back */
1523 switch (port->config.format) {
1525 copy_float_to_short((short *)(port->wr_cur+port->was_written), (const float *)data,
1526 block, !B_HOST_IS_LENDIAN == !port->config.big_endian);
1530 if (!B_HOST_IS_LENDIAN == !port->config.big_endian) {
1532 swap_copy((short *)(port->wr_cur+port->was_written), (const short *)data, block);
1539 memcpy((void *)(port->wr_cur+port->was_written), data, block);
1543 port->was_written += block;
1544 port->wr_silence = 0;
1546 release_spinlock(&port->wr_lock);
1555 release_sem(port->wr_entry);
1566 pcm_dev * port = &dev->pcm;
1574 ddprintf(("cmedia_pci: dma_a 0x%x+0x%x\n", PCI_IO_RD_32((int)port->dma_a), PCI_IO_RD_32((int)port->dma_a+4)));
1577 acquire_spinlock(&port->wr_lock);
1579 if (port->write_sem < 0) {
1581 release_spinlock(&port->wr_lock);
1586 if (port->was_written > 0 && port->was_written < port->wr_size) {
1587 if (port->config.format == 0x11) {
1588 memset((void *)(port->wr_cur+port->was_written), 0x80, port->wr_size-port->was_written);
1591 memset((void *)(port->wr_cur+port->was_written), 0, port->wr_size-port->was_written);
1599 addr = PCI_IO_RD_32((uint32)port->dma_a);
1600 if ((offs = addr-(uint32)port->card->low_phys) < port->wr_size) {
1601 ptr = port->wr_2;
1604 ptr = port->wr_1;
1606 port->wr_total += port->config.play_buf_size/2;
1609 port->wr_time = st-(offs&(port->config.play_buf_size/2-1))*250000LL/(int64)port->config.sample_rate;
1610 if ((ww = atomic_add(&port->wr_time_wait, -1)) > 0) {
1611 release_sem_etc(port->wr_time_sem, 1, B_DO_NOT_RESCHEDULE);
1615 atomic_add(&port->wr_time_wait, 1); /* re-set to 0 */
1618 if (port->wr_cur == ptr) {
1619 port->wr_skipped++;
1620 OLDAPI(("cmedia_pci: write skipped %ld\n", port->wr_skipped));
1622 port->wr_cur = ptr;
1623 port->was_written = 0;
1627 if (atomic_add(&port->write_waiting, -1) > 0) {
1632 release_sem_etc(port->write_sem, 1, B_DO_NOT_RESCHEDULE);
1636 atomic_add(&port->write_waiting, 1);
1638 if (port->wr_silence < (int32)port->config.play_buf_size * 2) {
1639 if (port->config.format == 0x11) {
1640 memset((void *)ptr, 0x80, port->wr_size);
1643 memset((void *)ptr, 0, port->wr_size);
1645 port->wr_silence += port->wr_size;
1650 release_spinlock(&port->wr_lock);
1660 pcm_dev * port = &dev->pcm;
1669 ddprintf(("cmedia_pci: dma_c 0x%x+0x%x\n", PCI_IO_RD_32((int)port->dma_c), PCI_IO_RD_32((int)port->dma_c+4)));
1672 acquire_spinlock(&port->rd_lock);
1674 if (port->read_sem < 0) {
1676 release_spinlock(&port->rd_lock);
1681 addr = PCI_IO_RD_32((uint32)port->dma_c);
1682 if ((offs = addr-port->config.play_buf_size-(uint32)port->card->low_phys) < port->rd_size) {
1683 ptr = port->rd_2;
1686 ptr = port->rd_1;
1688 if (port->rd_cur == ptr) {
1689 port->rd_skipped++;
1690 OLDAPI(("cmedia_pci: read skipped %ld\n", port->rd_skipped));
1692 port->rd_total += port->rd_size;
1694 port->rd_cur = ptr;
1695 port->was_read = 0;
1696 port->rd_time = port->next_rd_time;
1698 port->next_rd_time = st-(offs&(port->config.rec_buf_size/2-1))*1000000LL/(int64)port->config.sample_rate;
1699 if ((rr = atomic_add(&port->rd_time_wait, -1)) > 0) {
1700 release_sem_etc(port->rd_time_sem, 1, B_DO_NOT_RESCHEDULE);
1704 atomic_add(&port->rd_time_wait, 1); /* re-set to 0 */
1707 if (atomic_add(&port->read_waiting, -1) > 0) {
1708 release_sem_etc(port->read_sem, 1, B_DO_NOT_RESCHEDULE);
1712 atomic_add(&port->read_waiting, 1);
1715 release_spinlock(&port->rd_lock);