ac97/auvia/auvia.c

178 	auvia_reg_write_32(&stream->card->config, stream->base + AUVIA_RP_DMAOPS_BASE,
189 		if(stream->base != AUVIA_8233_MP_BASE) {
190 			value = auvia_reg_read_32(&stream->card->config, stream->base
199 			auvia_reg_write_32(&stream->card->config, stream->base
206 			auvia_reg_write_8(&stream->card->config, stream->base
208 			auvia_reg_write_32(&stream->card->config, stream->base
241 		addr = auvia_reg_read_32(&stream->card->config, stream->base + AUVIA_RP_DMAOPS_BASE);
245 		addr = auvia_reg_read_32(&stream->card->config, stream->base + AUVIA_RP_DMAOPS_BASE);
263 		if(stream->base != AUVIA_8233_MP_BASE) {
264 			auvia_reg_write_8(&stream->card->config, stream->base + AUVIA_8233_RP_DXS_LVOL, 0);
265 			auvia_reg_write_8(&stream->card->config, stream->base + AUVIA_8233_RP_DXS_RVOL, 0);
267 		auvia_reg_write_8(&stream->card->config, stream->base + AUVIA_RP_CONTROL,
274 		auvia_reg_write_8(&stream->card->config, stream->base + AUVIA_RP_MODE, regvalue);
275 		auvia_reg_write_8(&stream->card->config, stream->base + AUVIA_RP_CONTROL,
288 	auvia_reg_write_8(&stream->card->config, stream->base + AUVIA_RP_CONTROL,
320 			stream->base = AUVIA_8233_MP_BASE;
321 			//stream->base = AUVIA_PLAY_BASE;
323 			stream->base = AUVIA_PLAY_BASE;
326 			stream->base = AUVIA_8233_RECORD_BASE;
328 			stream->base = AUVIA_RECORD_BASE;
362 	auvia_reg_write_32(&stream->card->config, stream->base + AUVIA_RP_DMAOPS_BASE, 0);
391 			if(auvia_reg_read_8(&card->config, stream->base + AUVIA_RP_STAT) & AUVIA_RPSTAT_INTR) {
407 				auvia_reg_write_8(&card->config, stream->base + AUVIA_RP_STAT, AUVIA_RPSTAT_INTR);