busses/agp_gart/intel_gart.cpp

37 #define get_pci_config(info, offset, size) \
38 	(sPCI->read_pci_config((info).bus, (info).device, (info).function, \
40 #define set_pci_config(info, offset, size, value) \
41 	(sPCI->write_pci_config((info).bus, (info).device, (info).function, \
248 has_display_device(pci_info &info, uint32 deviceID)
250 	for (uint32 index = 0; sPCI->get_nth_pci_info(index, &info) == B_OK;
252 		if (info.vendor_id != VENDOR_ID_INTEL
253 			|| info.device_id != deviceID
254 			|| info.class_base != PCI_display)
265 gtt_memory_config(intel_info &info)
268 	if (info.type->Generation() >= 6)
271 	return get_pci_config(info.bridge, controlRegister, 2);
276 determine_gtt_stolen(intel_info &info)
278 	uint16 memoryConfig = gtt_memory_config(info);
281 	if (info.type->InGroup(INTEL_GROUP_83x)) {
298 	} else if (info.type->InGroup(INTEL_GROUP_SNB)
299 		|| info.type->InGroup(INTEL_GROUP_IVB)
300 		|| info.type->InGroup(INTEL_GROUP_HAS)) {
351 	} else if (info.type->InGroup(INTEL_GROUP_BDW)
352 		|| info.type->InFamily(INTEL_FAMILY_LAKE)) {
409 		if(info.type->InGroup(INTEL_GROUP_BDW)) {
413 		} else if(info.type->InFamily(INTEL_FAMILY_LAKE)) {
462 	} else if (info.type->InGroup(INTEL_GROUP_85x)
463 		|| info.type->InFamily(INTEL_FAMILY_9xx)
464 		|| info.type->InGroup(INTEL_GROUP_ILK)) {
512 determine_gtt_size(intel_info &info)
514 	uint16 memoryConfig = gtt_memory_config(info);
517 	if (info.type->IsModel(INTEL_MODEL_965)) {
529 	} else if (info.type->IsModel(INTEL_MODEL_G33)
530 	           || info.type->InGroup(INTEL_GROUP_PIN)) {
539 	} else if (info.type->InGroup(INTEL_GROUP_G4x)
540 			|| info.type->InGroup(INTEL_GROUP_ILK)) {
559 	} else if (info.type->InGroup(INTEL_GROUP_SNB)
560 			|| info.type->InGroup(INTEL_GROUP_IVB)
561 			|| info.type->InGroup(INTEL_GROUP_HAS)) {
573 	} else if (info.type->InGroup(INTEL_GROUP_BDW)
574 			|| info.type->InFamily(INTEL_FAMILY_LAKE)) {
593 		if (info.type->InFamily(INTEL_FAMILY_8xx)) {
594 			if (info.type->InGroup(INTEL_GROUP_83x)
599 		} else if (info.type->Generation() >= 3) {
600 			frameBufferSize = info.display.u.h0.base_register_sizes[2];
611 set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress)
613 	if (info.type->Generation() >= 8) {
617 	} else if (info.type->Generation() >= 6) {
621 	} else if (info.type->Generation() >= 4) {
629 	write32(info.gtt_base + (offset >> GTT_PAGE_SHIFT),
635 intel_unmap(intel_info &info)
637 	delete_area(info.registers_area);
638 	delete_area(info.gtt_area);
639 	delete_area(info.scratch_area);
640 	delete_area(info.aperture_area);
641 	info.aperture_size = 0;
646 intel_map(intel_info &info)
650 	if (info.type->Generation() >= 3) {
657 	phys_addr_t addr = info.display.u.h0.base_registers[mmioIndex];
658 	uint64 barSize = info.display.u.h0.base_register_sizes[mmioIndex];
659 	if ((info.display.u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) {
660 		addr |= (uint64)info.display.u.h0.base_registers[mmioIndex + 1] << 32;
661 		barSize |= (uint64)info.display.u.h0.base_register_sizes[mmioIndex + 1] << 32;
665 	info.registers_area = mmioMapper.Map("intel GMCH mmio", addr, barSize,
666 		B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers);
670 		return info.registers_area;
674 	set_pci_config(info.display, PCI_command, 2,
675 		get_pci_config(info.display, PCI_command, 2)
680 	info.scratch_area = scratchCreator.Create("intel GMCH scratch",
685 		return info.scratch_area;
693 	if (info.type->InFamily(INTEL_FAMILY_8xx)) {
694 		info.gtt_physical_base = read32(info.registers
696 		if (info.gtt_physical_base == 0) {
700 			info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
703 	} else if (info.type->InGroup(INTEL_GROUP_91x)) {
704 		info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
707 		info.gtt_physical_base = addr + (2UL << 20);
710 	size_t gttSize = determine_gtt_size(info);
711 	size_t stolenSize = determine_gtt_stolen(info);
713 	info.gtt_entries = gttSize / 4096;
714 	info.gtt_stolen_entries = stolenSize / 4096;
717 		info.gtt_physical_base, gttSize, info.gtt_entries, stolenSize);
720 	info.gtt_area = gttMapper.Map("intel GMCH gtt",
721 		info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS,
722 		B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.gtt_base);
725 		return info.gtt_area;
728 	info.aperture_physical_base = info.display.u.h0.base_registers[fbIndex];
729 	info.aperture_stolen_size = stolenSize;
730 	if ((info.display.u.h0.base_register_flags[fbIndex] & PCI_address_type) == PCI_address_type_64) {
731 		info.aperture_physical_base |= (uint64)info.display.u.h0.base_registers[fbIndex + 1] << 32;
732 		if (info.aperture_size == 0) {
733 			info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex]
734 				|= (uint64)info.display.u.h0.base_register_sizes[fbIndex + 1] << 32;
736 	} else if (info.aperture_size == 0)
737 		info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex];
741 		info.aperture_size >> 20, gttSize >> 10);
743 	ERROR("GTT base = 0x%" B_PRIxPHYSADDR "\n", info.gtt_physical_base);
745 		info.display.u.h0.base_registers[mmioIndex]);
746 	ERROR("GMR base = 0x%" B_PRIxPHYSADDR "\n", info.aperture_physical_base);
749 	info.aperture_area = apertureMapper.Map("intel graphics aperture",
750 		info.aperture_physical_base, info.aperture_size,
752 		B_READ_AREA | B_WRITE_AREA, (void**)&info.aperture_base);
757 		info.aperture_area = apertureMapper.Map("intel graphics aperture",
758 			info.aperture_physical_base, info.aperture_size,
760 			(void**)&info.aperture_base);
764 		return info.aperture_area;
767 	info.scratch_page = entry.address;
827 intel_get_aperture_info(void* aperture, aperture_info* info)
829 	if (info == NULL)
832 	info->base = sInfo.aperture_base;
833 	info->physical_base = sInfo.aperture_physical_base;
834 	info->size = sInfo.aperture_size;
835 	info->reserved_size = sInfo.aperture_stolen_size;