bus_managers/pci/pci_info.cpp

33 print_pci2pci_bridge_info(const pci_info *info, bool verbose)
36 		info->u.h1.subsystem_id, info->u.h1.subsystem_vendor_id));
38 		" secondary_latency %02x\n", info->u.h1.primary_bus,
39 		info->u.h1.secondary_bus, info->u.h1.subordinate_bus, info->u.h1.secondary_latency));
40 	uint32 io_base = ((uint32)info->u.h1.io_base & 0xf0) << 8;
41 	if (info->u.h1.io_base & 1)
42 		 io_base += ((uint32)info->u.h1.io_base_upper16 << 16);
43 	uint32 io_limit = (((uint32)info->u.h1.io_limit & 0xf0) << 8) + 0xfff;
44 	if (info->u.h1.io_limit & 1)
45 		 io_limit += info->u.h1.io_limit_upper16 << 16;
48 	uint32 memory_base = ((uint32)info->u.h1.memory_base & 0xfff0) << 16;
49 	uint32 memory_limit = (((uint32)info->u.h1.memory_limit & 0xfff0) << 16)
54 		((uint32)info->u.h1.prefetchable_memory_base & 0xfff0) << 16;
55 	if (info->u.h1.prefetchable_memory_base & 1) {
57 			(uint64)info->u.h1.prefetchable_memory_base_upper32 << 32;
60 		(((uint32)info->u.h1.prefetchable_memory_limit & 0xfff0) << 16)
62 	if (info->u.h1.prefetchable_memory_limit & 1) {
64 			(uint64)info->u.h1.prefetchable_memory_limit_upper32 << 32;
69 			info->u.h1.bridge_control, info->u.h1.secondary_status));
71 			info->u.h1.interrupt_line, info->u.h1.interrupt_pin));
73 			info->u.h1.rom_base, info->u.h1.rom_base_pci));
76 			"size %08" B_PRIx32 ", flags %02x\n", i, info->u.h1.base_registers[i],
77 			info->u.h1.base_registers_pci[i], info->u.h1.base_register_sizes[i],
78 			info->u.h1.base_register_flags[i]));
83 print_pci2cardbus_bridge_info(const pci_info *info, bool verbose)
86 		info->u.h2.subsystem_id, info->u.h2.subsystem_vendor_id));
88 		"secondary_latency %02x\n", info->u.h2.primary_bus,
89 		info->u.h2.secondary_bus, info->u.h2.subordinate_bus,
90 		info->u.h2.secondary_latency));
92 		info->u.h2.bridge_control, info->u.h2.secondary_status));
94 		B_PRIx32 "\n", info->u.h2.memory_base_upper32, info->u.h2.memory_base));
96 		B_PRIx32 "\n", info->u.h2.memory_limit_upper32, info->u.h2.memory_limit));
98 		info->u.h2.io_base_upper32, info->u.h2.io_base));
100 		info->u.h2.io_limit_upper32, info->u.h2.io_limit));
105 print_generic_info(const pci_info *info, bool verbose)
108 		"%08" B_PRIx32 "\n", info->u.h0.rom_base, info->u.h0.rom_base_pci,
109 		info->u.h0.rom_size));
111 		"subsystem_vendor_id %04x\n", info->u.h0.cardbus_cis,
112 		info->u.h0.subsystem_id, info->u.h0.subsystem_vendor_id));
114 		"max_latency %02x\n", info->u.h0.interrupt_line, info->u.h0.interrupt_pin,
115 		info->u.h0.min_grant, info->u.h0.max_latency));
117 		if ((info->u.h0.base_register_flags[i] & PCI_address_type) == PCI_address_type_64) {
120 				info->u.h0.base_registers[i] | ((uint64)info->u.h0.base_registers[i + 1] << 32),
121 				info->u.h0.base_registers_pci[i] | ((uint64)info->u.h0.base_registers_pci[i + 1] << 32),
122 				info->u.h0.base_register_sizes[i] | ((uint64)info->u.h0.base_register_sizes[i + 1] << 32),
123 				info->u.h0.base_register_flags[i], info->u.h0.base_register_flags[i + 1]));
127 				"size %08" B_PRIx32 ", flags %02x\n", i, info->u.h0.base_registers[i],
128 				info->u.h0.base_registers_pci[i], info->u.h0.base_register_sizes[i],
129 				info->u.h0.base_register_flags[i]));
136 print_capabilities(const pci_info *info)
145 	status = pci_read_config(info->bus, info->device, info->function, PCI_status, 2);
151 	switch (info->header_type & PCI_header_type_mask) {
154 			cap_ptr = pci_read_config(info->bus, info->device, info->function, PCI_capabilities_ptr, 1);
157 			cap_ptr = pci_read_config(info->bus, info->device, info->function, PCI_capabilities_ptr_2, 1);
172 		cap_id  = pci_read_config(info->bus, info->device, info->function, cap_ptr, 1);
173 		cap_ptr = pci_read_config(info->bus, info->device, info->function, cap_ptr + 1, 1);
192 print_extended_capabilities(const pci_info *info)
194 	if (pci_find_capability(info->bus, info->device, info->function,
199 	uint32 capability = pci_read_config(info->bus, info->device,
200 		info->function, capPointer, 4);
222 		capability = pci_read_config(info->bus, info->device, info->function,
231 print_info_basic(const pci_info *info, bool verbose)
236 	__pci_resolve_virtual_bus(info->bus, &domain, &bus);
239 			domain, bus, info->bus /* virtual bus*/,
240 			info->device, info->function, info->vendor_id, info->device_id, info->revision));
242 			info->class_base, info->class_sub, info->class_api));
248 		get_vendor_info(info->vendor_id, &venShort, &venFull);
250 			TRACE(("PCI:   vendor %04x: Unknown\n", info->vendor_id));
252 			TRACE(("PCI:   vendor %04x: %s - %s\n", info->vendor_id, venShort, venFull));
254 			TRACE(("PCI:   vendor %04x: %s\n", info->vendor_id, venShort ? venShort : venFull));
258 		get_device_info(info->vendor_id, info->device_id, info->u.h0.subsystem_vendor_id, info->u.h0.subsystem_id,
261 			TRACE(("PCI:   device %04x: Unknown\n", info->device_id));
263 			TRACE(("PCI:   device %04x: %s (%s)\n", info->device_id, devShort, devFull));
265 			TRACE(("PCI:   device %04x: %s\n", info->device_id, devShort ? devShort : devFull));
268 		get_class_info(info->class_base, info->class_sub, info->class_api, classInfo, sizeof(classInfo));
269 		TRACE(("PCI:   info: %s\n", classInfo));
273 			info->line_size, info->latency, info->header_type, info->bist));
275 	switch (info->header_type & PCI_header_type_mask) {
277 			print_generic_info(info, verbose);
280 			print_pci2pci_bridge_info(info, verbose);
283 			print_pci2cardbus_bridge_info(info, verbose);
289 	print_capabilities(info);
290 	print_extended_capabilities(info);
297 	pci_info info;
298 	for (long index = 0; B_OK == pci_get_nth_pci_info(index, &info); index++) {
299 		print_info_basic(&info, PCI_VERBOSE);