Lines Matching refs:info
142 // info about device
153 // info about device
159 // info about device
222 // info about device
233 // info about device
239 // info about device
780 *outInfo = dev->info;
999 if (dev->info.class_base == PCI_bridge
1000 && dev->info.class_sub == PCI_pci
1001 && (dev->info.header_type & PCI_header_type_mask)
1059 if (dev->info.class_base == PCI_bridge
1060 && dev->info.class_sub == PCI_pci) {
1200 memset(&newDev->info, 0, sizeof(newDev->info));
1205 "class_sub 0x%02x\n", newDev->info.vendor_id, newDev->info.device_id,
1206 newDev->info.class_base, newDev->info.class_sub);
1328 dev->info.vendor_id = ReadConfig(dev->domain, dev->bus, dev->device,
1330 dev->info.device_id = ReadConfig(dev->domain, dev->bus, dev->device,
1332 dev->info.bus = virtualBus;
1333 dev->info.device = dev->device;
1334 dev->info.function = dev->function;
1335 dev->info.revision = ReadConfig(dev->domain, dev->bus, dev->device,
1337 dev->info.class_api = ReadConfig(dev->domain, dev->bus, dev->device,
1339 dev->info.class_sub = ReadConfig(dev->domain, dev->bus, dev->device,
1341 dev->info.class_base = ReadConfig(dev->domain, dev->bus, dev->device,
1343 dev->info.line_size = ReadConfig(dev->domain, dev->bus, dev->device,
1345 dev->info.latency = ReadConfig(dev->domain, dev->bus, dev->device,
1349 dev->info.header_type = ReadConfig(dev->domain, dev->bus, dev->device,
1351 dev->info.bist = ReadConfig(dev->domain, dev->bus, dev->device,
1353 dev->info.reserved = 0;
1360 switch (dev->info.header_type & PCI_header_type_mask) {
1372 _GetRomBarInfo(dev, PCI_rom_base, dev->info.u.h0.rom_base_pci,
1373 &dev->info.u.h0.rom_size);
1376 dev->info.u.h0.base_registers[i],
1377 dev->info.u.h0.base_registers_pci[i],
1378 dev->info.u.h0.base_register_sizes[i],
1379 dev->info.u.h0.base_register_flags[i],
1380 i < 5 ? &dev->info.u.h0.base_registers[i + 1] : NULL,
1381 i < 5 ? &dev->info.u.h0.base_registers_pci[i + 1] : NULL,
1382 i < 5 ? &dev->info.u.h0.base_register_sizes[i + 1] : NULL);
1389 dev->info.u.h0.rom_base = (uint32)pci_ram_address(
1390 dev->info.u.h0.rom_base_pci);
1392 dev->info.u.h0.cardbus_cis = ReadConfig(dev->domain, dev->bus,
1394 dev->info.u.h0.subsystem_id = ReadConfig(dev->domain, dev->bus,
1396 dev->info.u.h0.subsystem_vendor_id = ReadConfig(dev->domain,
1399 dev->info.u.h0.interrupt_line = ReadConfig(dev->domain, dev->bus,
1401 dev->info.u.h0.interrupt_pin = ReadConfig(dev->domain, dev->bus,
1403 dev->info.u.h0.min_grant = ReadConfig(dev->domain, dev->bus,
1405 dev->info.u.h0.max_latency = ReadConfig(dev->domain, dev->bus,
1421 dev->info.u.h1.rom_base_pci);
1424 dev->info.u.h1.base_registers[i],
1425 dev->info.u.h1.base_registers_pci[i],
1426 dev->info.u.h1.base_register_sizes[i],
1427 dev->info.u.h1.base_register_flags[i],
1428 i < 1 ? &dev->info.u.h1.base_registers[i + 1] : NULL,
1429 i < 1 ? &dev->info.u.h1.base_registers_pci[i + 1] : NULL,
1430 i < 1 ? &dev->info.u.h1.base_register_sizes[i + 1] : NULL);
1437 dev->info.u.h1.rom_base = (uint32)pci_ram_address(
1438 dev->info.u.h1.rom_base_pci);
1440 dev->info.u.h1.primary_bus = ReadConfig(dev->domain, dev->bus,
1442 dev->info.u.h1.secondary_bus = ReadConfig(dev->domain, dev->bus,
1444 dev->info.u.h1.subordinate_bus = ReadConfig(dev->domain,
1446 dev->info.u.h1.secondary_latency = ReadConfig(dev->domain,
1448 dev->info.u.h1.io_base = ReadConfig(dev->domain, dev->bus,
1450 dev->info.u.h1.io_limit = ReadConfig(dev->domain, dev->bus,
1452 dev->info.u.h1.secondary_status = ReadConfig(dev->domain,
1454 dev->info.u.h1.memory_base = ReadConfig(dev->domain, dev->bus,
1456 dev->info.u.h1.memory_limit = ReadConfig(dev->domain, dev->bus,
1458 dev->info.u.h1.prefetchable_memory_base = ReadConfig(dev->domain,
1461 dev->info.u.h1.prefetchable_memory_limit = ReadConfig(
1464 dev->info.u.h1.prefetchable_memory_base_upper32 = ReadConfig(
1467 dev->info.u.h1.prefetchable_memory_limit_upper32 = ReadConfig(
1470 dev->info.u.h1.io_base_upper16 = ReadConfig(dev->domain,
1472 dev->info.u.h1.io_limit_upper16 = ReadConfig(dev->domain,
1474 dev->info.u.h1.interrupt_line = ReadConfig(dev->domain, dev->bus,
1476 dev->info.u.h1.interrupt_pin = ReadConfig(dev->domain, dev->bus,
1478 dev->info.u.h1.bridge_control = ReadConfig(dev->domain, dev->bus,
1480 dev->info.u.h1.subsystem_id = ReadConfig(dev->domain, dev->bus,
1482 dev->info.u.h1.subsystem_vendor_id = ReadConfig(dev->domain,
1490 dev->info.u.h2.subsystem_id = ReadConfig(dev->domain, dev->bus,
1492 dev->info.u.h2.subsystem_vendor_id = ReadConfig(dev->domain,
1494 dev->info.u.h2.primary_bus = ReadConfig(dev->domain, dev->bus,
1496 dev->info.u.h2.secondary_bus = ReadConfig(dev->domain, dev->bus,
1498 dev->info.u.h2.subordinate_bus = ReadConfig(dev->domain,
1500 dev->info.u.h2.secondary_latency = ReadConfig(dev->domain,
1502 dev->info.u.h2.reserved = 0;
1503 dev->info.u.h2.memory_base = ReadConfig(dev->domain, dev->bus,
1505 dev->info.u.h2.memory_limit = ReadConfig(dev->domain, dev->bus,
1507 dev->info.u.h2.memory_base_upper32 = ReadConfig(dev->domain,
1509 dev->info.u.h2.memory_limit_upper32 = ReadConfig(dev->domain,
1511 dev->info.u.h2.io_base = ReadConfig(dev->domain, dev->bus,
1513 dev->info.u.h2.io_limit = ReadConfig(dev->domain, dev->bus,
1515 dev->info.u.h2.io_base_upper32 = ReadConfig(dev->domain,
1517 dev->info.u.h2.io_limit_upper32 = ReadConfig(dev->domain,
1519 dev->info.u.h2.secondary_status = ReadConfig(dev->domain,
1521 dev->info.u.h2.bridge_control = ReadConfig(dev->domain,
1527 TRACE(("PCI: Header type unknown (0x%02x)\n", dev->info.header_type));
1560 domain_data *info = _GetDomainData(domain);
1561 if (!info)
1564 if (device > (info->max_bus_devices - 1)
1574 return (*info->controller->read_pci_config)(info->controller_cookie, bus,
1608 domain_data *info = _GetDomainData(domain);
1609 if (!info)
1612 if (device > (info->max_bus_devices - 1)
1622 return (*info->controller->write_pci_config)(info->controller_cookie, bus,
1844 pci_info &info = device->info;
1845 switch (info.header_type & PCI_header_type_mask) {
1847 info.u.h0.interrupt_line = newInterruptLineValue;
1851 info.u.h1.interrupt_line = newInterruptLineValue;
1926 msi_info *info = &device->msi;
1927 if (!info->msi_capable)
1930 return info->message_count;
1943 msi_info *info = &device->msi;
1944 if (!info->msi_capable)
1947 if (count > 32 || count > info->message_count
1952 if (info->configured_count != 0)
1955 status_t result = msi_allocate_vectors(count, &info->start_vector,
1956 &info->address_value, &info->data_value);
1960 uint8 offset = info->capability_offset;
1962 info->address_value & 0xffffffff);
1963 if (info->control_value & PCI_msi_control_64bit) {
1965 info->address_value >> 32);
1967 info->data_value);
1969 WriteConfig(device, offset + PCI_msi_data, 2, info->data_value);
1971 info->control_value &= ~PCI_msi_control_mme_mask;
1972 info->control_value |= (ffs(count) - 1) << 4;
1973 WriteConfig(device, offset + PCI_msi_control, 2, info->control_value);
1975 info->configured_count = count;
1976 *startVector = info->start_vector;
1992 msi_info *info = &device->msi;
1993 if (!info->msi_capable)
1996 if (info->configured_count == 0)
1999 msi_free_vectors(info->configured_count, info->start_vector);
2001 info->control_value &= ~PCI_msi_control_mme_mask;
2002 WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
2003 info->control_value);
2005 info->configured_count = 0;
2006 info->address_value = 0;
2007 info->data_value = 0;
2018 msi_info *info = &device->msi;
2019 if (!info->msi_capable)
2022 if (info->configured_count == 0)
2030 info->control_value |= PCI_msi_control_enable;
2031 WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
2032 info->control_value);
2035 _HtMSIMap(device, info->address_value);
2038 ReadConfig(device, info->capability_offset + PCI_msi_control, 2));
2054 msi_info *info = &device->msi;
2055 if (!info->msi_capable)
2058 if (info->configured_count == 0)
2065 info->control_value &= ~PCI_msi_control_enable;
2066 WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
2067 info->control_value);
2079 msix_info *info = &device->msix;
2080 if (!info->msix_capable)
2083 return info->message_count;
2096 msix_info *info = &device->msix;
2097 if (!info->msix_capable)
2100 if (count > 32 || count > info->message_count) {
2104 if (info->configured_count != 0)
2108 size_t tableSize = info->message_count * 16;
2110 phys_addr_t barAddr = device->info.u.h0.base_registers[info->table_bar];
2111 uchar flags = device->info.u.h0.base_register_flags[info->table_bar];
2113 barAddr |= (uint64)device->info.u.h0.base_registers[
2114 info->table_bar + 1] << 32;
2117 barAddr, tableSize + info->table_offset,
2122 info->table_area_id = area;
2123 info->table_address = address + info->table_offset;
2126 if (info->table_bar != info->pba_bar) {
2127 barAddr = device->info.u.h0.base_registers[info->pba_bar];
2128 flags = device->info.u.h0.base_register_flags[info->pba_bar];
2130 barAddr |= (uint64)device->info.u.h0.base_registers[
2131 info->pba_bar + 1] << 32;
2134 barAddr, tableSize + info->pba_offset,
2138 delete_area(info->table_area_id);
2139 info->table_area_id = -1;
2142 info->pba_area_id = area;
2144 info->pba_area_id = -1;
2145 info->pba_address = address + info->pba_offset;
2147 status_t result = msi_allocate_vectors(count, &info->start_vector,
2148 &info->address_value, &info->data_value);
2150 delete_area(info->pba_area_id);
2151 delete_area(info->table_area_id);
2152 info->pba_area_id = -1;
2153 info->table_area_id = -1;
2161 uint32 data_value = info->data_value;
2163 volatile uint32 *entry = (uint32*)(info->table_address + 16 * index);
2165 *entry++ = info->address_value & 0xffffffff;
2166 *entry++ = info->address_value >> 32;
2171 info->configured_count = count;
2172 *startVector = info->start_vector;
2184 msix_info *info = &device->msix;
2185 if (!info->msix_capable)
2188 if (info->configured_count == 0)
2196 info->control_value |= PCI_msix_control_enable;
2197 WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
2198 info->control_value);
2201 _HtMSIMap(device, info->address_value);
2204 ReadConfig(device, info->capability_offset + PCI_msix_control, 2));
2212 ht_mapping_info *info = &device->ht_mapping;
2213 if (!info->ht_mapping_capable)
2216 bool enabled = (info->control_value & PCI_ht_command_msi_enable) != 0;
2219 info->control_value &= ~PCI_ht_command_msi_enable;
2221 if ((address >> 20) != (info->address_value >> 20))
2224 info->control_value |= PCI_ht_command_msi_enable;
2226 WriteConfig(device, info->capability_offset + PCI_ht_command, 2,
2227 info->control_value);
2238 msi_info *info = &device->msi;
2239 info->msi_capable = false;
2242 &info->capability_offset);
2246 info->msi_capable = true;
2247 info->control_value = ReadConfig(device->domain, device->bus,
2249 info->capability_offset + PCI_msi_control, 2);
2250 info->message_count
2251 = 1 << ((info->control_value & PCI_msi_control_mmc_mask) >> 1);
2252 info->configured_count = 0;
2253 info->data_value = 0;
2254 info->address_value = 0;
2264 msix_info *info = &device->msix;
2265 info->msix_capable = false;
2268 &info->capability_offset);
2272 info->msix_capable = true;
2273 info->control_value = ReadConfig(device->domain, device->bus,
2275 info->capability_offset + PCI_msix_control, 2);
2276 info->message_count
2277 = (info->control_value & PCI_msix_control_table_size) + 1;
2278 info->configured_count = 0;
2279 info->data_value = 0;
2280 info->address_value = 0;
2281 info->table_area_id = -1;
2282 info->pba_area_id = -1;
2285 info->capability_offset + PCI_msix_table, 4);
2288 info->capability_offset + PCI_msix_pba, 4);
2290 info->table_bar = table_value & PCI_msix_bir_mask;
2291 info->table_offset = table_value & PCI_msix_offset_mask;
2292 info->pba_bar = pba_value & PCI_msix_bir_mask;
2293 info->pba_offset = pba_value & PCI_msix_offset_mask;
2303 ht_mapping_info *info = &device->ht_mapping;
2304 info->ht_mapping_capable = false;
2309 info->control_value = ReadConfig(device, offset + PCI_ht_command,
2311 info->capability_offset = offset;
2312 info->ht_mapping_capable = true;
2313 if ((info->control_value & PCI_ht_command_msi_fixed) != 0) {
2315 info->address_value = MSI_ADDRESS_BASE;
2319 info->address_value = 0;
2322 info->address_value = ReadConfig(device, offset
2324 info->address_value <<= 32;
2325 info->address_value |= ReadConfig(device, offset
2329 info->address_value);
2337 msix_info *info = &device->msix;
2338 if (!info->msix_capable)
2341 if (info->configured_count == 0)
2345 info->control_value &= ~PCI_msix_control_enable;
2346 WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
2347 info->control_value);
2349 msi_free_vectors(info->configured_count, info->start_vector);
2350 for (uint8 index = 0; index < info->configured_count; index++) {
2351 volatile uint32 *entry = (uint32*)(info->table_address + 16 * index);
2356 if (info->pba_area_id != -1)
2357 delete_area(info->pba_area_id);
2358 if (info->table_area_id != -1)
2359 delete_area(info->table_area_id);
2360 info->pba_area_id= -1;
2361 info->table_area_id = -1;
2363 info->configured_count = 0;
2364 info->address_value = 0;
2365 info->data_value = 0;
2373 msix_info *info = &device->msix;
2374 if (!info->msix_capable)
2377 if (info->configured_count == 0)
2384 info->control_value &= ~PCI_msix_control_enable;
2385 gPCI->WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
2386 info->control_value);