bus_managers/pci/pci.cpp

44 pci_read_config(uint8 virtualBus, uint8 device, uint8 function, uint16 offset,
54 	if (gPCI->ReadConfig(domain, bus, device, function, offset, size,
63 pci_write_config(uint8 virtualBus, uint8 device, uint8 function, uint16 offset,
71 	gPCI->WriteConfig(domain, bus, device, function, offset, size, value);
93 pci_find_capability(uint8 virtualBus, uint8 device, uint8 function,
101 	return gPCI->FindCapability(domain, bus, device, function, capID, offset);
106 pci_find_extended_capability(uint8 virtualBus, uint8 device, uint8 function,
114 	return gPCI->FindExtendedCapability(domain, bus, device, function, capID,
120 pci_reserve_device(uchar virtualBus, uchar device, uchar function,
126 	TRACE(("pci_reserve_device(%d, %d, %d, %s)\n", virtualBus, device, function,
139 	//	domain, bus, device, function, driverName, nodeCookie));
142 		// info about device
148 		{B_PCI_DEVICE_DEVICE, B_UINT8_TYPE, {.ui8 = device}},
153 		// info about device
159 		// info about device
206 pci_unreserve_device(uchar virtualBus, uchar device, uchar function,
212 	TRACE(("pci_unreserve_device(%d, %d, %d, %s)\n", virtualBus, device,
219 	//	domain, bus, device, function, driverName, nodeCookie));
222 		// info about device
228 		{B_PCI_DEVICE_DEVICE, B_UINT8_TYPE, {.ui8 = device}},
233 		// info about device
239 		// info about device
290 pci_update_interrupt_line(uchar virtualBus, uchar device, uchar function,
298 	return gPCI->UpdateInterruptLine(domain, bus, device, function,
304 pci_get_powerstate(uchar virtualBus, uint8 device, uint8 function, uint8* state)
311 	return gPCI->GetPowerstate(domain, bus, device, function, state);
316 pci_set_powerstate(uchar virtualBus, uint8 device, uint8 function, uint8 newState)
323 	return gPCI->SetPowerstate(domain, bus, device, function, newState);
503 	add_debugger_command("pcistatus", &pcistatus, "dump and clear pci device status registers");
750 PCI::_NumFunctions(uint8 domain, uint8 bus, uint8 device)
752 	uint8 type = ReadConfig(domain, bus, device,
1004 				dev->device, dev->function, PCI_bridge_control, 2);
1016 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1018 			bridgeControlNew = ReadConfig(dev->domain, dev->bus, dev->device,
1022 				dev->device, dev->function, bridgeControlOld,
1036 		// Clear and dump PCI device status
1037 		uint16 status = ReadConfig(dev->domain, dev->bus, dev->device,
1039 		WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1042 			kprintf("domain %u, bus %u, dev %2u, func %u, PCI device status "
1043 				"0x%04x\n", dev->domain, dev->bus, dev->device, dev->function,
1063 				dev->device, dev->function, PCI_secondary_status, 2);
1064 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1069 					dev->device, dev->function, secondaryStatus);
1086 				dev->device, dev->function, PCI_bridge_control, 2);
1087 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1091 					"control 0x%04x\n", dev->domain, dev->bus, dev->device,
1184 PCI::_CreateDevice(PCIBus *parent, uint8 device, uint8 function)
1187 		parent->bus, device, function);
1198 	newDev->device = device;
1204 	FLOW("PCI: CreateDevice, vendor 0x%04x, device 0x%04x, class_base 0x%02x, "
1241 	uint64 pciAddress = ReadConfig(dev->domain, dev->bus, dev->device,
1243 	WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1245 	uint64 size = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1247 	WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1259 				dev->device, dev->function, offset + 4, 4);
1260 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1262 			uint64 highSize = ReadConfig(dev->domain, dev->bus, dev->device,
1264 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1301 	uint32 oldValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1303 	WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1305 	uint32 newValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1307 	WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1328 	dev->info.vendor_id = ReadConfig(dev->domain, dev->bus, dev->device,
1330 	dev->info.device_id = ReadConfig(dev->domain, dev->bus, dev->device,
1333 	dev->info.device = dev->device;
1335 	dev->info.revision = ReadConfig(dev->domain, dev->bus, dev->device,
1337 	dev->info.class_api = ReadConfig(dev->domain, dev->bus, dev->device,
1339 	dev->info.class_sub = ReadConfig(dev->domain, dev->bus, dev->device,
1341 	dev->info.class_base = ReadConfig(dev->domain, dev->bus, dev->device,
1343 	dev->info.line_size = ReadConfig(dev->domain, dev->bus, dev->device,
1345 	dev->info.latency = ReadConfig(dev->domain, dev->bus, dev->device,
1349 	dev->info.header_type = ReadConfig(dev->domain, dev->bus, dev->device,
1351 	dev->info.bist = ReadConfig(dev->domain, dev->bus, dev->device,
1363 			// disable PCI device address decoding (io and memory) while BARs
1365 			uint16 pcicmd = ReadConfig(dev->domain, dev->bus, dev->device,
1367 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1385 			// restore PCI device address decoding
1386 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1393 				dev->device, dev->function, PCI_cardbus_cis, 4);
1395 				dev->device, dev->function, PCI_subsystem_id, 2);
1397 				dev->bus, dev->device, dev->function, PCI_subsystem_vendor_id,
1400 				dev->device, dev->function, PCI_interrupt_line, 1);
1402 				dev->device, dev->function, PCI_interrupt_pin, 1);
1404 				dev->device, dev->function, PCI_min_grant, 1);
1406 				dev->device, dev->function, PCI_max_latency, 1);
1412 			// disable PCI device address decoding (io and memory) while BARs
1414 			uint16 pcicmd = ReadConfig(dev->domain, dev->bus, dev->device,
1416 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1433 			// restore PCI device address decoding
1434 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1441 				dev->device, dev->function, PCI_primary_bus, 1);
1443 				dev->device, dev->function, PCI_secondary_bus, 1);
1445 				dev->bus, dev->device, dev->function, PCI_subordinate_bus, 1);
1447 				dev->bus, dev->device, dev->function, PCI_secondary_latency, 1);
1449 				dev->device, dev->function, PCI_io_base, 1);
1451 				dev->device, dev->function, PCI_io_limit, 1);
1453 				dev->bus, dev->device, dev->function, PCI_secondary_status, 2);
1455 				dev->device, dev->function, PCI_memory_base, 2);
1457 				dev->device, dev->function, PCI_memory_limit, 2);
1459 				dev->bus, dev->device, dev->function,
1462 				dev->domain, dev->bus, dev->device, dev->function,
1465 				dev->domain, dev->bus, dev->device, dev->function,
1468 				dev->domain, dev->bus, dev->device, dev->function,
1471 				dev->bus, dev->device, dev->function, PCI_io_base_upper16, 2);
1473 				dev->bus, dev->device, dev->function, PCI_io_limit_upper16, 2);
1475 				dev->device, dev->function, PCI_interrupt_line, 1);
1477 				dev->device, dev->function, PCI_interrupt_pin, 1);
1479 				dev->device, dev->function, PCI_bridge_control, 2);
1481 				dev->device, dev->function, PCI_sub_device_id_1, 2);
1483 				dev->bus, dev->device, dev->function, PCI_sub_vendor_id_1, 2);
1491 				dev->device, dev->function, PCI_sub_device_id_2, 2);
1493 				dev->bus, dev->device, dev->function, PCI_sub_vendor_id_2, 2);
1495 				dev->device, dev->function, PCI_primary_bus_2, 1);
1497 				dev->device, dev->function, PCI_secondary_bus_2, 1);
1499 				dev->bus, dev->device, dev->function, PCI_subordinate_bus_2, 1);
1501 				dev->bus, dev->device, dev->function, PCI_secondary_latency_2, 1);
1504 				dev->device, dev->function, PCI_memory_base0_2, 4);
1506 				dev->device, dev->function, PCI_memory_limit0_2, 4);
1508 				dev->bus, dev->device, dev->function, PCI_memory_base1_2, 4);
1510 				dev->bus, dev->device, dev->function, PCI_memory_limit1_2, 4);
1512 				dev->device, dev->function, PCI_io_base0_2, 4);
1514 				dev->device, dev->function, PCI_io_limit0_2, 4);
1516 				dev->bus, dev->device, dev->function, PCI_io_base1_2, 4);
1518 				dev->bus, dev->device, dev->function, PCI_io_limit1_2, 4);
1520 				dev->bus, dev->device, dev->function, PCI_secondary_status_2, 2);
1522 				dev->bus, dev->device, dev->function, PCI_bridge_control_2, 2);
1557 PCI::ReadConfig(uint8 domain, uint8 bus, uint8 device, uint8 function,
1564 	if (device > (info->max_bus_devices - 1)
1569 		dprintf("PCI: can't read config for domain %d, bus %u, device %u, function %u, offset %u, size %u\n",
1570 			 domain, bus, device, function, offset, size);
1575 		device, function, offset, size, value);
1580 PCI::ReadConfig(uint8 domain, uint8 bus, uint8 device, uint8 function,
1584 	if (ReadConfig(domain, bus, device, function, offset, size, &value)
1593 PCI::ReadConfig(PCIDev *device, uint16 offset, uint8 size)
1596 	if (ReadConfig(device->domain, device->bus, device->device,
1597 			device->function, offset, size, &value) != B_OK)
1605 PCI::WriteConfig(uint8 domain, uint8 bus, uint8 device, uint8 function,
1612 	if (device > (info->max_bus_devices - 1)
1617 		dprintf("PCI: can't write config for domain %d, bus %u, device %u, function %u, offset %u, size %u\n",
1618 			 domain, bus, device, function, offset, size);
1623 		device, function, offset, size, value);
1628 PCI::WriteConfig(PCIDev *device, uint16 offset, uint8 size, uint32 value)
1630 	return WriteConfig(device->domain, device->bus, device->device,
1631 		device->function, offset, size, value);
1636 PCI::FindCapability(uint8 domain, uint8 bus, uint8 device, uint8 function,
1639 	uint16 status = ReadConfig(domain, bus, device, function, PCI_status, 2);
1642 			"not supported\n", bus, device, function, capID);
1646 	uint8 headerType = ReadConfig(domain, bus, device, function,
1660 				"%#02x unknown header type\n", bus, device, function, capID);
1664 	capPointer = ReadConfig(domain, bus, device, function, capPointer, 1);
1668 			"empty list\n", bus, device, function, capID);
1673 		if (ReadConfig(domain, bus, device, function, capPointer, 1) == capID) {
1679 		capPointer = ReadConfig(domain, bus, device, function, capPointer + 1,
1687 	TRACE_CAP("PCI: find_pci_capability ERROR %u:%u:%u capability %#02x circular list\n", bus, device, function, capID);
1693 PCI::FindCapability(PCIDev *device, uint8 capID, uint8 *offset)
1695 	return FindCapability(device->domain, device->bus, device->device,
1696 		device->function, capID, offset);
1701 PCI::FindExtendedCapability(uint8 domain, uint8 bus, uint8 device,
1704 	if (FindCapability(domain, bus, device, function, PCI_cap_id_pcie)
1707 			"not supported\n", bus, device, function, capID);
1711 	uint32 capability = ReadConfig(domain, bus, device, function,
1727 		capability = ReadConfig(domain, bus, device, function,
1732 		"circular list\n", bus, device, function, capID);
1738 PCI::FindExtendedCapability(PCIDev *device, uint16 capID, uint16 *offset)
1740 	return FindExtendedCapability(device->domain, device->bus, device->device,
1741 		device->function, capID, offset);
1746 PCI::FindHTCapability(uint8 domain, uint8 bus, uint8 device,
1753 		capPointer = ReadConfig(domain, bus, device, function, *offset + 1,
1755 	} else if (FindCapability(domain, bus, device, function, PCI_cap_id_ht,
1758 			"not supported\n", bus, device, function, capID);
1770 		uint8 capability = ReadConfig(domain, bus, device, function,
1773 			if ((ReadConfig(domain, bus, device, function,
1781 		capPointer = ReadConfig(domain, bus, device, function, capPointer + 1,
1786 		"circular list\n", bus, device, function, capID);
1792 PCI::FindHTCapability(PCIDev *device, uint16 capID, uint8 *offset)
1794 	return FindHTCapability(device->domain, device->bus, device->device,
1795 		device->function, capID, offset);
1800 PCI::FindDevice(uint8 domain, uint8 bus, uint8 device, uint8 function)
1805 	return _FindDevice(fDomainData[domain].bus, domain, bus, device, function);
1810 PCI::_FindDevice(PCIBus *current, uint8 domain, uint8 bus, uint8 device,
1814 		// search device on this bus
1818 			if (child->bus == bus && child->device == device
1824 				PCIDev *found = _FindDevice(child->child, domain, bus, device,
1840 	PCIDev *device = FindDevice(domain, bus, _device, function);
1841 	if (device == NULL)
1844 	pci_info &info = device->info;
1858 	return WriteConfig(device, PCI_interrupt_line, 1, newInterruptLineValue);
1863 PCI::GetPowerstate(PCIDev *device)
1866 	status_t res = FindCapability(device, PCI_cap_id_pm, &capabilityOffset);
1868 		uint32 state = ReadConfig(device, capabilityOffset + PCI_pm_status, 2);
1876 PCI::SetPowerstate(PCIDev *device, uint8 newState)
1879 	status_t res = FindCapability(device, PCI_cap_id_pm, &capabilityOffset);
1881 		uint32 state = ReadConfig(device, capabilityOffset + PCI_pm_status, 2);
1883 			WriteConfig(device, capabilityOffset + PCI_pm_status, 2,
1896 	PCIDev *device = FindDevice(domain, bus, _device, function);
1897 	if (device == NULL)
1900 	*state = GetPowerstate(device);
1909 	PCIDev *device = FindDevice(domain, bus, _device, function);
1910 	if (device == NULL)
1913 	SetPowerstate(device, newState);
1921 PCI::GetMSICount(PCIDev *device)
1926 	msi_info *info = &device->msi;
1935 PCI::ConfigureMSI(PCIDev *device, uint32 count, uint32 *startVector)
1943 	msi_info *info = &device->msi;
1961 	WriteConfig(device, offset + PCI_msi_address, 4,
1964 		WriteConfig(device, offset + PCI_msi_address_high, 4,
1966 		WriteConfig(device, offset + PCI_msi_data_64bit, 2,
1969 		WriteConfig(device, offset + PCI_msi_data, 2, info->data_value);
1973 	WriteConfig(device, offset + PCI_msi_control, 2, info->control_value);
1982 PCI::UnconfigureMSI(PCIDev *device)
1988 	status_t result = _UnconfigureMSIX(device);
1992 	msi_info *info =  &device->msi;
2002 	WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
2013 PCI::EnableMSI(PCIDev *device)
2018 	msi_info *info =  &device->msi;
2026 	WriteConfig(device, PCI_command, 2,
2027 		ReadConfig(device, PCI_command, 2) | PCI_command_int_disable);
2031 	WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
2035 	_HtMSIMap(device, info->address_value);
2038 		ReadConfig(device, info->capability_offset + PCI_msi_control, 2));
2044 PCI::DisableMSI(PCIDev *device)
2050 	status_t result = _DisableMSIX(device);
2054 	msi_info *info =  &device->msi;
2062 	_HtMSIMap(device, 0);
2066 	WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
2074 PCI::GetMSIXCount(PCIDev *device)
2079 	msix_info *info = &device->msix;
2088 PCI::ConfigureMSIX(PCIDev *device, uint32 count, uint32 *startVector)
2096 	msix_info *info = &device->msix;
2110 	phys_addr_t barAddr = device->info.u.h0.base_registers[info->table_bar];
2111 	uchar flags = device->info.u.h0.base_register_flags[info->table_bar];
2113 		barAddr |= (uint64)device->info.u.h0.base_registers[
2127 		barAddr = device->info.u.h0.base_registers[info->pba_bar];
2128 		flags = device->info.u.h0.base_register_flags[info->pba_bar];
2130 			barAddr |= (uint64)device->info.u.h0.base_registers[
2158 	WriteConfig(device, PCI_command, 2,
2159 		ReadConfig(device, PCI_command, 2) | PCI_command_memory);
2179 PCI::EnableMSIX(PCIDev *device)
2184 	msix_info *info = &device->msix;
2192 	WriteConfig(device, PCI_command, 2,
2193 		ReadConfig(device, PCI_command, 2) | PCI_command_int_disable);
2197 	WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
2201 	_HtMSIMap(device, info->address_value);
2204 		ReadConfig(device, info->capability_offset + PCI_msix_control, 2));
2210 PCI::_HtMSIMap(PCIDev *device, uint64 address)
2212 	ht_mapping_info *info = &device->ht_mapping;
2226 		WriteConfig(device, info->capability_offset + PCI_ht_command, 2,
2233 PCI::_ReadMSIInfo(PCIDev *device)
2238 	msi_info *info = &device->msi;
2240 	status_t result = FindCapability(device->domain, device->bus,
2241 		device->device, device->function, PCI_cap_id_msi,
2247 	info->control_value = ReadConfig(device->domain, device->bus,
2248 		device->device, device->function,
2259 PCI::_ReadMSIXInfo(PCIDev *device)
2264 	msix_info *info = &device->msix;
2266 	status_t result = FindCapability(device->domain, device->bus,
2267 		device->device, device->function, PCI_cap_id_msix,
2273 	info->control_value = ReadConfig(device->domain, device->bus,
2274 		device->device, device->function,
2283 	uint32 table_value = ReadConfig(device->domain, device->bus,
2284 		device->device, device->function,
2286 	uint32 pba_value = ReadConfig(device->domain, device->bus,
2287 		device->device, device->function,
2298 PCI::_ReadHtMappingInfo(PCIDev *device)
2303 	ht_mapping_info *info = &device->ht_mapping;
2307 	if (FindHTCapability(device, PCI_ht_command_cap_msi_mapping,
2309 		info->control_value = ReadConfig(device, offset + PCI_ht_command,
2322 			info->address_value = ReadConfig(device, offset
2325 			info->address_value |= ReadConfig(device, offset
2335 PCI::_UnconfigureMSIX(PCIDev *device)
2337 	msix_info *info =  &device->msix;
2346 	WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
2371 PCI::_DisableMSIX(PCIDev *device)
2373 	msix_info *info =  &device->msix;
2381 	_HtMSIMap(device, 0);
2385 	gPCI->WriteConfig(device, info->capability_offset + PCI_msix_control, 2,