bus_managers/firewire/fwohci.cpp

830 #define LAST_DB(dbtr, db) do {						\
833 	db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0];			\
840 	struct fwohcidb *db;
847 	db = &db_tr->db[db_tr->dbcnt];
850 		FWOHCI_DMA_WRITE(db->db.desc.addr, bus_addr);
851 		FWOHCI_DMA_WRITE(db->db.desc.cmd, step);
852  		FWOHCI_DMA_WRITE(db->db.desc.res, 0);
854 		db++;
858 		FWOHCI_DMA_WRITE(db->db.desc.addr, bus_addr);
859 		FWOHCI_DMA_WRITE(db->db.desc.cmd, info->pay_len % step);
860  		FWOHCI_DMA_WRITE(db->db.desc.res, 0);
861 		db++;
884 	struct fwohcidb *db;
921 	ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
945 	db = &db_tr->db[0];
946  	FWOHCI_DMA_WRITE(db->db.desc.cmd,
948  	FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
949  	FWOHCI_DMA_WRITE(db->db.desc.res, 0);
952  		FWOHCI_DMA_WRITE(db->db.desc.res,
964 	db = &db_tr->db[db_tr->dbcnt];
1006 			FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1015 	/* last db */
1016 	LAST_DB(db_tr, db);
1017  	FWOHCI_DMA_SET(db->db.desc.cmd,
1019  	FWOHCI_DMA_WRITE(db->db.desc.depend,
1025 		LAST_DB(dbch->pdb_tr, db);
1026  		FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1083 	struct fwohcidb *db;
1105 		LAST_DB(tr, db);
1106 		status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1301 		db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1384 	struct fwohcidb *db;
1413 		db = db_tr->db;
1415 		FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1417 		db[ldesc].db.desc.depend = db[0].db.desc.depend;
1421 					db[ldesc].db.desc.cmd,
1425 					db[0].db.desc.cmd,
1432 		dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1443 	struct fwohcidb *db;
1518 		db = db_tr->db;
1520 		FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1525 					db[ldesc].db.desc.cmd,
1528 					db[ldesc].db.desc.depend,
1535 		dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1613 		struct fwohcidb *db;
1619 			db = ((struct fwohcidb_tr *)(prev->end))->db;
1621 			FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1625 			db[ldesc].db.desc.depend = db[0].db.desc.depend =
1629 			FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1630 			FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1743 		struct fwohcidb *db;
1752  			FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1757 		db = ((struct fwohcidb_tr *)(chunk->end))->db;
1758 		FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1759 		FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1761 			db = ((struct fwohcidb_tr *)(prev->end))->db;
1762 			FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
2174 	struct fwohcidb *db;
2188 		db = ((struct fwohcidb_tr *)(chunk->end))->db;
2189 		stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2191 		db = ((struct fwohcidb_tr *)(chunk->start))->db;
2193 		count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2239 		stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2361 	prev = pp->db;
2371 				curr = cp->db;
2373 					next = np->db;
2385 		prev = pp->db;
2406 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2413 	if(db == NULL){
2431 		cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2432 		res = FWOHCI_DMA_READ(db[i].db.desc.res);
2442 				FWOHCI_DMA_READ(db[i].db.desc.addr),
2443 				FWOHCI_DMA_READ(db[i].db.desc.depend),
2462 				FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2463 				FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2464 				FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2465 				FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2527 	struct fwohcidb *db;
2544 		db = db_tr->db;
2546 		ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2553 		FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2554 		FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2557 		FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2558 		FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2559 		FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2561 		db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2564 		db[0].db.desc.depend =
2565 			= db[dbch->ndesc - 1].db.desc.depend
2568 		FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2569 		FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2574 	db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2575 	FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2576 	FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2578 	db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2580 	db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2594 	struct fwohcidb *db = db_tr->db;
2606 	FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2608 	FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2609 	bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2610 	FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2613 	FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2616 	FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2617 	FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2627 	struct fwohcidb *db = db_tr->db;
2630 		FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2631 		FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2633 			FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2635 		FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2639 		FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2641 	FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2724 	struct fwohcidb *db = &db_tr->db[0];
2726 	FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2727 	FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2728 	FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2766 	status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2767 	resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2946 			status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2948 			resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2975 		resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)