accelerants/radeon_hd/connector.cpp

38 	gpio_info* info = (gpio_info*)cookie;
44 		if (info->i2c.hwCapable == true && gInfo->shared_info->dceMajor >= 3) {
46 			buffer = Read32(OUT, info->i2c.sclMaskReg);
48 			Write32(OUT, info->i2c.sclMaskReg, buffer);
52 		buffer = Read32(OUT, info->i2c.sclAReg) & ~info->i2c.sclAMask;
53 		Write32(OUT, info->i2c.sclAReg, buffer);
54 		buffer = Read32(OUT, info->i2c.sdaAReg) & ~info->i2c.sdaAMask;
55 		Write32(OUT, info->i2c.sdaAReg, buffer);
59 	buffer = Read32(OUT, info->i2c.sclEnReg) & ~info->i2c.sclEnMask;
60 	Write32(OUT, info->i2c.sclEnReg, buffer);
61 	buffer = Read32(OUT, info->i2c.sdaEnReg) & ~info->i2c.sdaEnMask;
62 	Write32(OUT, info->i2c.sdaEnReg, buffer);
65 	buffer = Read32(OUT, info->i2c.sclMaskReg);
67 		buffer |= info->i2c.sclMask;
69 		buffer &= ~info->i2c.sclMask;
71 	Write32(OUT, info->i2c.sclMaskReg, buffer);
72 	Read32(OUT, info->i2c.sclMaskReg);
75 	buffer = Read32(OUT, info->i2c.sdaMaskReg);
77 		buffer |= info->i2c.sdaMask;
79 		buffer &= ~info->i2c.sdaMask;
81 	Write32(OUT, info->i2c.sdaMaskReg, buffer);
82 	Read32(OUT, info->i2c.sdaMaskReg);
89 	gpio_info* info = (gpio_info*)cookie;
91 	uint32 scl = Read32(OUT, info->i2c.sclYReg) & info->i2c.sclYMask;
92 	uint32 sda = Read32(OUT, info->i2c.sdaYReg) & info->i2c.sdaYMask;
104 	gpio_info* info = (gpio_info*)cookie;
106 	uint32 scl = Read32(OUT, info->i2c.sclEnReg) & ~info->i2c.sclEnMask;
107 	scl |= clock ? 0 : info->i2c.sclEnMask;
108 	Write32(OUT, info->i2c.sclEnReg, scl);
109 	Read32(OUT, info->i2c.sclEnReg);
111 	uint32 sda = Read32(OUT, info->i2c.sdaEnReg) & ~info->i2c.sdaEnMask;
112 	sda |= data ? 0 : info->i2c.sdaEnMask;
113 	Write32(OUT, info->i2c.sdaEnReg, sda);
114 	Read32(OUT, info->i2c.sdaEnReg);
123 	radeon_shared_info &info = *gInfo->shared_info;
127 	if (info.dceMajor >= 4
132 		if (info.dceMajor >= 13) {
135 		} else if (info.dceMajor >= 12)
137 		else if (info.dceMajor >= 11)
139 		else if (info.dceMajor >= 10)
141 		else if (info.dceMajor >= 8)
143 		else if (info.dceMajor >= 6)
145 		else if (info.dceMajor >= 4)
220 		struct _ATOM_LVDS_INFO info;
237 			= B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usPixClk) * 10;
240 			= B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usHActive);
242 			lvdsInfo->info.sLCDTiming.usHBlanking_Time);
244 			+ B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usHSyncOffset);
246 			+ B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usHSyncWidth);
249 			= B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usVActive);
251 			lvdsInfo->info.sLCDTiming.usVBlanking_Time);
253 			+ B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usVSyncOffset);
255 			+ B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usVSyncWidth);
260 			= B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.usOffDelayInMs);
264 		gConnector[connectorIndex]->lvdsFlags = lvdsInfo->info.ucLVDS_Misc;
267 		gInfo->lvdsSpreadSpectrumID = lvdsInfo->info.ucSS_Id;
270 			lvdsInfo->info.sLCDTiming.susModeMiscInfo.usAccess);
428 	radeon_shared_info &info = *gInfo->shared_info;
475 		if (info.dceMajor >= 3) {
483 		if (info.dceMajor >= 4) {
578 		struct _ATOM_SUPPORTED_DEVICES_INFO info;
587 		= B_LENDIAN_TO_HOST_INT16(supportedDevices->info.usDeviceSupport);
613 			= supportedDevices->info.asConnInfo[i];
747 			radeon_shared_info &info = *gInfo->shared_info;
759 			if ((info.chipsetFlags & CHIP_IGP) != 0) {
1031 			// hot plug detection info
1038 			// router info
1056 			// encoder info