radeon_hd/atombios/atom.cpp

110 atom_iio_execute(atom_context *ctx, int base, uint32 index, uint32 data)
114 	switch(CU8(base)) {
116 			base++;
119 			temp = ctx->card->ioreg_read(CU16(base + 1));
120 			base += 3;
123 			(void)ctx->card->reg_read(CU16(base + 1));
124 			ctx->card->ioreg_write(CU16(base + 1), temp);
125 			base += 3;
128 			temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 2));
129 			base += 3;
132 			temp |= (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 2);
133 			base += 3;
136 			temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3));
137 			temp |= ((index >> CU8(base + 2))
138 				& (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 3);
139 			base += 4;
142 			temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3));
143 			temp |= ((data >> CU8(base + 2))
144 				& (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 3);
145 			base += 4;
148 			temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3));
149 			temp |= ((ctx->io_attr >> CU8(base + 2))
150 				& (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 3);
151 			base += 4;
1205 	int base = CU16(ctx->cmd_table + 4 + 2 * index);
1210 	if (!base) {
1215 	len = CU16(base + ATOM_CT_SIZE_PTR);
1216 	ws = CU8(base + ATOM_CT_WS_PTR);
1217 	ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
1218 	ptr = base + ATOM_CT_CODE_PTR;
1222 	ectx.start = base;
1308 atom_index_iio(atom_context *ctx, int base)
1311 	while (CU8(base) == ATOM_IIO_START) {
1312 		ctx->iio[CU8(base + 1)] = base + 2;
1313 		base += 2;
1314 		while (CU8(base) != ATOM_IIO_END)
1315 			base += atom_iio_len[CU8(base)];
1316 		base += 3;
1346 	int base = CU16(ATOM_ROM_TABLE_PTR);
1347 	if (strncmp(CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
1354 	ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
1355 	ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
1358 	char *str = CSTR(CU16(base + ATOM_ROM_MSG_PTR));