accelerants/radeon/monitor_routing.c

27 	accelerator_info *ai, routing_regs *values )
31 	values->dac_cntl = INREG( regs, RADEON_DAC_CNTL );
32 	values->dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
33 	values->crtc_ext_cntl = INREG( regs, RADEON_CRTC_EXT_CNTL );
34 	values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
35 	values->disp_output_cntl = INREG( regs, RADEON_DISP_OUTPUT_CNTL );
36 	values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );
37 	values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL );
47 		values->disp_hw_debug = INREG( regs, RADEON_DISP_HW_DEBUG );
51 		values->disp_tv_out_cntl = INREG( regs, RADEON_DISP_TV_OUT_CNTL );
59 		values->gpiopad_a = INREG( regs, RADEON_GPIOPAD_A );
68 		values->tv_dac_cntl = INREG( regs, RADEON_TV_DAC_CNTL );
72 		values->tv_master_cntl = INREG( regs, RADEON_TV_MASTER_CNTL );
74 	values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
75 	values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
81 	accelerator_info *ai, const impactv_params *tv_parameters, routing_regs *values )
100 	values->dac_cntl |=
105 	values->crtc_ext_cntl =
110 	values->dac_cntl &= ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING);
111 	values->dac_cntl |= RADEON_DAC_RANGE_CNTL_PS2;
114 	values->fp_gen_cntl &=
122 	values->fp_gen_cntl |=
131 		values->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
141 			values->dac_cntl2 &= ~RADEON_DAC_CLK_SEL_MASK;
142 			values->dac_cntl2 |= crtc_idx == 0 ? 0 : RADEON_DAC_CLK_SEL_CRTC2;
151 			values->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
152 			values->disp_output_cntl |=
161 		values->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
169 		values->tv_dac_cntl |=
180 		values->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
182 		values->dac_cntl2 &= ~RADEON_DAC2_CLK_SEL_MASK;
183 		values->dac_cntl2 |= RADEON_DAC2_CLK_SEL_CRT;
186 		values->tv_dac_cntl =
195 				values->gpiopad_a |= 1;
198 		values->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
201 	values->skip_tv_dac = false;
207 		values->dac_cntl &= ~RADEON_DAC_TVO_EN;
213 		values->dac_cntl2 &= ~RADEON_DAC2_CLK_SEL_MASK;
214 		values->dac_cntl2 |= RADEON_DAC2_CLK_SEL_TV;
218 				values->gpiopad_a &= ~1;
222 		values->skip_tv_dac = true;
226 			values->dac_cntl |= RADEON_DAC_TVO_EN;
232 			values->disp_output_cntl &=
242 			values->disp_output_cntl |=
247 			values->disp_output_cntl |= tv_parameters->mode888 ?
255 				values->disp_tv_out_cntl &=
272 				values->disp_tv_out_cntl |= RADEON_DISP_TV_CLKO_OUT_EN;
283 			values->tv_master_cntl =
303 					values->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
305 			values->disp_hw_debug |= crtc_idx == 0 ? RADEON_CRT2_DISP1_SEL : 0;
310 			values->disp_output_cntl |= RADEON_DISP_TV_SOURCE;
312 			values->disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC;
313 			values->disp_tv_out_cntl |= crtc_idx == 0 ? 0 : RADEON_DISP_TV_PATH_SRC;
321 			values->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
322 			values->disp_output_cntl |=
335 		values->pixclks_cntl &= ~RADEON_PIXCLK_TV_SRC_SEL_MASK;
336 		values->pixclks_cntl |= crtc_idx == 0 ?
347 		values->vclk_ecp_cntl &=
350 		values->vclk_ecp_cntl |= RADEON_VCLK_SRC_BYTE_CLK;
351 		values->vclk_ecp_cntl |= 0 << RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_SHIFT;
355 		values->vclk_ecp_cntl |= RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb;
359 		values->vclk_ecp_cntl &= ~RADEON_VCLK_SRC_SEL_MASK;
360 		values->vclk_ecp_cntl |= RADEON_VCLK_SRC_PPLL_CLK;
363 		values->vclk_ecp_cntl |= RADEON_PIXCLK_ALWAYS_ONb;
366 	values->pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
372 		values->pixclks_cntl |= 2;
374 		values->pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLL_CLK;
380 		values->fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
381 		values->fp_gen_cntl |= crtc_idx == 0 ? 0 : RADEON_FP_SEL_CRTC2;
388 		values->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
389 		values->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_RMX;
406 			values->fp2_gen_cntl &= ~RADEON_FP2_SOURCE_SEL_CRTC2;
407 		    values->fp2_gen_cntl |=
412 			values->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
413 			values->fp2_gen_cntl |=
420 	accelerator_info *ai, routing_regs *values )
424 	OUTREG( regs, RADEON_DAC_CNTL, values->dac_cntl );
425 	OUTREG( regs, RADEON_DAC_CNTL2, values->dac_cntl2 );
426 	OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc2_gen_cntl,
428 	OUTREG( regs, RADEON_DISP_OUTPUT_CNTL, values->disp_output_cntl );
438 		OUTREG( regs, RADEON_DISP_HW_DEBUG, values->disp_hw_debug );
442 		OUTREG( regs, RADEON_DISP_TV_OUT_CNTL, values->disp_tv_out_cntl );
450 		OUTREGP( regs, RADEON_GPIOPAD_A, values->gpiopad_a, ~1 );
461 		if( !values->skip_tv_dac )
462 			OUTREG( regs, RADEON_TV_DAC_CNTL, values->tv_dac_cntl );
466 		OUTREG( regs, RADEON_TV_MASTER_CNTL, values->tv_master_cntl );
468 	OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, ~(
481 	OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
486 			RADEON_VCLK_ECP_CNTL, values->vclk_ecp_cntl,
492 			RADEON_PIXCLKS_CNTL, values->pixclks_cntl,
497 		RADEON_PIXCLKS_CNTL, values->pixclks_cntl,
535 	OUTREGP( regs, RADEON_CRTC_EXT_CNTL, values->crtc_ext_cntl,