accelerants/radeon/impactv.c

127 // these values are not scaled
418 	impactv_params *params, impactv_regs *values, int crtc_idx,
428 	values->tv_ftotal = timing->f_total;
432 	values->tv_vscaler_cntl1 = RADEON_TV_VSCALER_CNTL1_Y_W_EN;
434 	values->tv_vscaler_cntl1 =
435 		(values->tv_vscaler_cntl1 & 0xe3ff0000) |
440 		values->tv_vscaler_cntl1 |= RADEON_TV_VSCALER_CNTL1_RESTART_FIELD;
442 			values->tv_vscaler_cntl1 |= 4 << RADEON_TV_VSCALER_CNTL1_Y_DEL_W_SIG_SHIFT;
444 			values->tv_vscaler_cntl1 |= 2 << RADEON_TV_VSCALER_CNTL1_Y_DEL_W_SIG_SHIFT;
446 		values->tv_vscaler_cntl1 |= 2 << RADEON_TV_VSCALER_CNTL1_Y_DEL_W_SIG_SHIFT;
449 	values->tv_y_saw_tooth_cntl =
453 	values->tv_y_fall_cntl =
459 	values->tv_y_rise_cntl =
463 	// RE: all dither flags/values were zero
464 	values->tv_vscaler_cntl2 =
465 		(values->tv_vscaler_cntl2 & 0x00fffff0) |
469 		values->tv_vscaler_cntl2 |=
476 	values->tv_hrestart = params->h_restart;
477 	values->tv_vrestart = params->v_restart;
478 	values->tv_frestart = params->f_restart;
480 	values->tv_tv_pll_cntl =
493 	values->tv_crt_pll_cntl =
506 	values->tv_clock_sel_cntl =
511     values->tv_clkout_cntl = 0x09;
513 		values->tv_clkout_cntl |= 1 << 5;
515 	values->tv_htotal = mode->timing.h_total - 1;
516 	values->tv_hsize = mode->timing.h_display;
517 	values->tv_hdisp = mode->timing.h_display - 1;
518 	values->tv_hstart =
520 		values->tv_hdisp + 1 - params->mode888 + 12;
522 	values->tv_vtotal = mode->timing.v_total - 1;
523 	values->tv_vdisp = mode->timing.v_display - 1;
524 	values->tv_sync_size = mode->timing.h_display + 8;
526 	values->tv_timing_cntl =
527 		(values->tv_timing_cntl & 0xfffff000) |
533 		values->tv_timing_cntl =
534 			(values->tv_timing_cntl & 0x00ffffff) |
541 		values->tv_dac_cntl =
549 			values->tv_dac_cntl |= RADEON_TV_DAC_CNTL_STD_NTSC;
557 			values->tv_dac_cntl |= RADEON_TV_DAC_CNTL_STD_PAL;
564 		values->tv_dac_cntl |=
570 			values->tv_dac_cntl &=
575 			values->tv_dac_cntl &=
580 		values->tv_dac_cntl =
581 			(values->tv_dac_cntl & ~(RADEON_TV_DAC_CNTL_STD_NTSC | 0x88 |
588 	values->tv_modulator_cntl1 &= ~(
597 		//values->tv_dac_cntl |=
598 		values->tv_modulator_cntl1 |=
602 		values->tv_modulator_cntl2 =
608 		values->tv_modulator_cntl1 |=
613 		values->tv_modulator_cntl2 =
620 		values->tv_modulator_cntl1 |=
623 		values->tv_modulator_cntl2 =
634     values->tv_modulator_cntl1 |=
641 		values->tv_data_delay_a = 0x0b0c0a06;
642 		values->tv_data_delay_b = 0x070a0a0c;
644 		values->tv_data_delay_a = 0x07080604;
645 		values->tv_data_delay_b = 0x03070607;
648 	values->tv_frame_lock_cntl = internal_encoder ? 0 : 0xf0f;
651 		values->tv_pll_cntl1 =
659 		values->tv_rgb_cntl =
666 		values->tv_rgb_cntl |= 0x4000000;
668 		values->tv_pre_dac_mux_cntl =
679 		values->tv_pll_cntl1 =
684 		values->tv_rgb_cntl = params->mode888;
686 		values->tv_pre_dac_mux_cntl =
695 	values->tv_pll_fine_cntl = 0;
699 	values->tv_master_cntl =
704 		values->tv_master_cntl |= RADEON_TV_MASTER_CNTL_RESTART_PHASE_FIX;
706 		values->tv_master_cntl &= ~RADEON_TV_MASTER_CNTL_RESTART_PHASE_FIX;
710 		values->tv_master_cntl |= RADEON_TV_MASTER_CNTL_TV_ON;
712 		values->tv_master_cntl |=
719 	values->tv_gain_limit_settings = 0x017f05ff;
720 	values->tv_linear_gain_settings = 0x01000100;
721 	values->tv_upsamp_and_gain_cntl = 0x00000005;
722 	values->tv_crc_cntl = 0;
724 	SHOW_FLOW( 2, "tv_master_cntl=%x", values->tv_master_cntl );
726 	memcpy( values->tv_upsample_filter_coeff, std_upsample_filter_coeff,
730 	memcpy( values->tv_hor_timing, hor_timings[tv_format-1],
732 	memcpy( values->tv_vert_timing, vert_timings[tv_format-1],
736 	values->tv_uv_adr = TV_UV_ADR_INI;
742 	impactv_regs *values, bool internal_encoder )
744 	switch( (values->tv_uv_adr & RADEON_TV_UV_ADR_HCODE_TABLE_SEL_MASK)
751 		return ((values->tv_uv_adr & RADEON_TV_UV_ADR_TABLE1_BOT_ADR_MASK)
754 		return ((values->tv_uv_adr & RADEON_TV_UV_ADR_TABLE3_TOP_ADR_MASK)
764 	impactv_regs *values )
766 	switch( (values->tv_uv_adr & RADEON_TV_UV_ADR_VCODE_TABLE_SEL_MASK)
770 		return ((values->tv_uv_adr & RADEON_TV_UV_ADR_MAX_UV_ADR_MASK)
774 		return ((values->tv_uv_adr & RADEON_TV_UV_ADR_TABLE1_BOT_ADR_MASK)
778 		return ((values->tv_uv_adr & RADEON_TV_UV_ADR_TABLE3_TOP_ADR_MASK)
789 	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values, bool internal_encoder )
791 	uint16 addr = getHorTimingTableAddr( values, internal_encoder );
796 			((uint32)values->tv_hor_timing[i] << 14) |
797 			values->tv_hor_timing[i + 1];
801 		if( values->tv_hor_timing[i] == 0 ||
802 			values->tv_hor_timing[i + 1] == 0 )
810 	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values )
812 	uint16 addr = getVertTimingTableAddr( values );
817 			((uint32)values->tv_vert_timing[i + 1] << 14) |
818 			values->tv_vert_timing[i];
822 		if( values->tv_vert_timing[i + 1] == 0 ||
823 			values->tv_vert_timing[i] == 0 )