accelerants/radeon/flat_panel.c

21 	accelerator_info *ai, fp_regs *values )
25 	values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH );
26 	values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH );
30 	fp_info *flatpanel, display_mode *mode, bool use_rmx, fp_regs *values )
38 		values->fp_horz_stretch &=
42 		values->fp_vert_stretch &=
62 	values->fp_horz_stretch = flatpanel->panel_xres << RADEON_HORZ_PANEL_SIZE_SHIFT;
65 		values->fp_horz_stretch &=
74 		values->fp_horz_stretch = stretch
75 			| (values->fp_horz_stretch & (RADEON_HORZ_PANEL_SIZE |
78 		values->fp_horz_stretch |=
82 	values->fp_horz_stretch &= ~RADEON_HORZ_AUTO_RATIO;
84 	values->fp_vert_stretch = flatpanel->panel_yres << RADEON_VERT_PANEL_SIZE_SHIFT;
87 		values->fp_vert_stretch &=
96 		values->fp_vert_stretch = stretch
97 			| (values->fp_vert_stretch & (RADEON_VERT_PANEL_SIZE |
99 		values->fp_vert_stretch |=
103 	values->fp_vert_stretch &= ~RADEON_VERT_AUTO_RATIO_EN;
108 	accelerator_info *ai, fp_regs *values )
112 	OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch );
113 	OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch );
118 	accelerator_info *ai, fp_regs *values )
122 	values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
123 	values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
124 	values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL );
125 	values->tmds_pll_cntl = INREG( regs, RADEON_TMDS_PLL_CNTL );
126 	values->tmds_trans_cntl = INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL );
127 	values->fp_h_sync_strt_wid = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );
128 	values->fp_v_sync_strt_wid = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );
129 	values->fp2_h_sync_strt_wid = INREG( regs, RADEON_FP_H2_SYNC_STRT_WID );
130 	values->fp2_v_sync_strt_wid = INREG( regs, RADEON_FP_V2_SYNC_STRT_WID );
131 	values->bios_4_scratch =  INREG( regs, RADEON_BIOS_4_SCRATCH );
132 	values->bios_5_scratch =  INREG( regs, RADEON_BIOS_5_SCRATCH );
133 	values->bios_6_scratch =  INREG( regs, RADEON_BIOS_6_SCRATCH );
137 		values->tmds_pll_cntl ^= (1 << 22);
141     		values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch,
142     		values->lvds_gen_cntl );
149 	fp_info *fp_port, crtc_regs *crtc_values, fp_regs *values )
152 	uint32 tmp = values->tmds_pll_cntl & 0xfffff;
155 	// (most values are ignored according to fp_gen_cntl, but at least polarity
159 		values->fp2_h_sync_strt_wid = crtc_values->crtc_h_sync_strt_wid;
160 		values->fp2_v_sync_strt_wid = crtc_values->crtc_v_sync_strt_wid;
163 		values->fp_h_sync_strt_wid = crtc_values->crtc_h_sync_strt_wid;
164 		values->fp_v_sync_strt_wid = crtc_values->crtc_v_sync_strt_wid;
168 		// should retain POST values (esp bit 28)
169 		values->fp2_gen_cntl &= (0xFFFF0000);
173 		values->fp_gen_cntl &=
181 		values->fp_gen_cntl |=
197 			values->tmds_pll_cntl = tmp;
199 			values->tmds_pll_cntl = ai->si->tmds_pll_cntl & 0xfff00000;
200 			values->tmds_pll_cntl |= tmp;
203 		values->tmds_pll_cntl = tmp;
206 	values->tmds_trans_cntl = ai->si->tmds_transmitter_cntl
210 		values->tmds_trans_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
212 		values->tmds_trans_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
219 		values->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
220 		values->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
225 		values->fp_gen_cntl |= RADEON_FP_FPON | RADEON_FP_TMDS_EN;
227 		values->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;
232 		values->fp2_gen_cntl |= RADEON_FP2_FPON | RADEON_FP_PANEL_FORMAT;
233 		values->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
236 		//values->fp2_gen_cntl |= (1 << 22) | (1 << 28);
239 			values->fp2_gen_cntl |= RADEON_FP2_DV0_EN;
243     	values->fp_gen_cntl, values->fp2_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch,
244     	values->lvds_gen_cntl );
251 	fp_info *fp_port, fp_regs *values )
258 	OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, RADEON_FP_SEL_CRTC2 );
262 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
264 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
266 		OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid );
267 		OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid );
270 		OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid );
271 		OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid );
282 		OUTREG( regs, RADEON_BIOS_4_SCRATCH, values->bios_4_scratch);
283 		OUTREG( regs, RADEON_BIOS_5_SCRATCH, values->bios_5_scratch);
284 		OUTREG( regs, RADEON_BIOS_6_SCRATCH, values->bios_6_scratch);
289 		//OUTREGP( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl,
300 			if (!(values->lvds_gen_cntl & RADEON_LVDS_ON)) {
310 			( values->lvds_gen_cntl & ( RADEON_LVDS_ON | RADEON_LVDS_BLON ))) {
311 			OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );
313 			if ( values->lvds_gen_cntl & ( RADEON_LVDS_ON | RADEON_LVDS_BLON )) {
315 				OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );
319 				OUTREG( regs, RADEON_LVDS_GEN_CNTL,	values->lvds_gen_cntl | RADEON_LVDS_BLON );
321 				OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );
326 			if (!(values->lvds_gen_cntl & RADEON_LVDS_ON)) {