accelerants/intel_extreme/Ports.cpp

1032 	FDILink* link = fPipe->FDI();
1033 	if (link != NULL) {
1037 		link->PreTrain(&target->timing, &linkBandwidth, &lanes, &bitsPerPixel);
1039 		link->Train(&target->timing, lanes);
1277 	FDILink* link = fPipe->FDI();
1278 	if (link != NULL) {
1282 		link->PreTrain(&hardwareTarget, &linkBandwidth, &lanes, &bitsPerPixel);
1284 		link->Train(&hardwareTarget, lanes);
1480 	FDILink* link = fPipe->FDI();
1481 	if (link != NULL) {
1485 		link->PreTrain(&target->timing, &linkBandwidth, &lanes, &bitsPerPixel);
1487 		link->Train(&target->timing, lanes);
1756 		TRACE("%s: %s link not detected\n", __func__, PortName());
1760 	TRACE("%s: %s link detected\n", __func__, PortName());
1850 	TRACE("%s: DP M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_M + fPipeOffset));
1851 	TRACE("%s: DP N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_N + fPipeOffset));
1870 	//Set TU size bits (to default, max) before link training so that error detection works
1894 	TRACE("%s: DP M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_M + fPipeOffset));
1895 	TRACE("%s: DP N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_PIPE_A_LINK_N + fPipeOffset));
1907 	TRACE("%s: DP link reference clock is %gMhz\n", __func__, linkBandwidth / 1000.0f);
1923 	TRACE("%s: DP M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset));
1924 	TRACE("%s: DP N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset));
1942 			ERROR("%s: DP illegal link colordepth set.\n", __func__);
1945 	TRACE("%s: DP link colordepth: %" B_PRIu32 "\n", __func__, bitsPerPixel);
1960 		//Note that we *must* abort as otherwise the PIPE/DP-link hangs forever (without retraining!).
1979 	//Set TU size bits (to default, max) before link training so that error detection works
2003 	TRACE("%s: DP M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_M1 + fPipeOffset));
2004 	TRACE("%s: DP N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_TRANSCODER_A_LINK_N1 + fPipeOffset));
2074 				FDILink* link = fPipe->FDI();
2075 				if (link != NULL) {
2076 					link->PreTrain(&hardwareTarget, &linkBandwidth, &lanes, &bitsPerPixel);
2078 					link->Train(&hardwareTarget, lanes);
2166 		TRACE("%s: %s link not detected\n", __func__, PortName());
2494 					ERROR("%s: DDI No known DP-link reference clock selected, assuming default\n", __func__);
2498 			ERROR("%s: DDI No known PLL selected, assuming default DP-link reference\n", __func__);
2501 	TRACE("%s: DDI DP-link reference clock is %gMhz\n", __func__, linkBandwidth / 1000.0f);
2520 	TRACE("%s: DDI M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset));
2521 	TRACE("%s: DDI N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset));
2539 			ERROR("%s: DDI illegal link colordepth set.\n", __func__);
2568 	//Set TU size bits (to default, max) before link training so that error detection works
2592 	TRACE("%s: DDI M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset));
2593 	TRACE("%s: DDI N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset));