Lines Matching refs:mode

74 CalculateCrtcRegisters(const DisplayModeEx& mode, DisplayParams& params)
76 // Define CRTC registers for requested video mode.
83 switch (mode.bitsPerPixel) {
97 TRACE("Unsupported color depth: %d bits/pixel\n", mode.bitsPerPixel);
105 params.crtc_h_total_disp = (((mode.timing.h_total / 8) - 1) & 0xffff)
106 | (((mode.timing.h_display / 8) - 1) << 16);
108 int hSyncWidth = (mode.timing.h_sync_end - mode.timing.h_sync_start) / 8;
114 int hSyncStart = mode.timing.h_sync_start - 8 + hSyncFudge[format - 1];
117 | ((mode.timing.flags & B_POSITIVE_HSYNC) ? 0 : R128_CRTC_H_SYNC_POL);
119 params.crtc_v_total_disp = (((mode.timing.v_total - 1) & 0xffff)
120 | ((mode.timing.v_display - 1) << 16));
122 int vSyncWidth = mode.timing.v_sync_end - mode.timing.v_sync_start;
128 params.crtc_v_sync_strt_wid = ((mode.timing.v_sync_start - 1) & 0xfff)
130 | ((mode.timing.flags & B_POSITIVE_VSYNC) ? 0 : R128_CRTC_V_SYNC_POL);
132 params.crtc_pitch = mode.timing.h_display / 8;
139 CalculateDDARegisters(const DisplayModeEx& mode, DisplayParams& params)
141 // Compute and write DDA registers for requested video mode.
155 int bytesPerPixel = (mode.bitsPerPixel + 7) / 8;
191 CalculatePLLRegisters(const DisplayModeEx& mode, DisplayParams& params)
193 // Define PLL registers for requested video mode.
216 uint32 freq = mode.timing.pixel_clock / 10;
353 Rage128_SetDisplayMode(const DisplayModeEx& mode)
357 // and assume that the mode values we get here are acceptable.
364 if ( ! CalculateCrtcRegisters(mode, params))
367 if ( ! CalculatePLLRegisters(mode, params))
370 if ( ! CalculateDDARegisters(mode, params))
378 uint16 vesaMode = GetVesaModeNumber(display_mode(mode), mode.bitsPerPixel);
387 Rage128_AdjustFrame(mode);
400 Rage128_EngineInit(mode);
408 Rage128_AdjustFrame(const DisplayModeEx& mode)
414 int address = (mode.v_display_start * mode.virtual_width
415 + mode.h_display_start) * ((mode.bitsPerPixel + 1) / 8);
428 // Set the indexed color palette for 8-bit color depth mode.