config/rs6000/rs6000.c

139   enum rs6000_abi abi;		/* which ABI to use */
206 /* Counter for labels which are to be placed in .fixup.  */
291 /* Masks to determine which reciprocal esitmate instructions to generate
381    into real registers, and skip the ANY class, which is just an OR of the
400    compiler has been more restrictive which types can do PRE_MODIFY instead of
1121 /* Support for -mveclibabi=<xxx> to control which vector library to use.  */
3029   /* Calculate which modes to automatically generate code to use a the
3196 /* Return the builtin mask of the various options used that could affect which
3821      target attribute or pragma which automatically enables both options,
3893      clear a possible request for string instructions, not supported and which
4304   /* Set the builtin mask of the various options used that could affect which
5385    depends on STEP and COPIES, one of which will be 1.  If COPIES > 1,
5439   /* Also check if are loading up the most significant bit which can be done by
6828   /* Recognize the rtl generated by reload which we know will later be
7431       /* We currently use relocations like @got@tlsgd for tls, which
7623   /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7975    sub-words of a TFmode operand, which is what we had before.  */
8967   /* Above, we may have called force_const_mem which may have returned
9250    int_size_in_bytes returns -1 for variable size objects, which go in
9496 /* If defined, a C expression which determines whether, and in which
9713 	  /* We couldn't find an appropriate mode, which happens,
9774 	       which works on arbitrarily large groups of int-type
10179 	  /* We couldn't find an appropriate mode, which happens,
10296    Much of this is taken from the SPARC V9 port, which has a similar
10372        (subreg:SI (reg:DF) 4), which are not handled well.  The code to
10470    or a hard register in which to store the argument.
10476    CUM is a variable of type CUMULATIVE_ARGS which gives info about
10991     /* Must be a libcall, all of which only use reg parms.  */
11153 	     the bytes, only those to which we actually will save
14030       /* We need to get to the OV bit, which is the ORDERED bit.  We
17500    which in turn calls this function, to do whatever is necessary to create
17984 	 On Darwin, pic addresses require a load from memory, which
19821 /* Return the string to output a conditional branch to LABEL, which is
19850   /* Work out which way this really branches.  We could use
19865       /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
20289      Inf - Inf is NaN which is not zero, and so if we don't
20655    which to shift and mask.  */
20910    to perform.  MEM is the memory on which to operate.  VAL is the second
21440 	 stack for it, if it looks like we're calling SAVE_WORLD, which
21786    reason is early versions of powerpc-linux which didn't properly
21830   /* Select which calling sequence.  */
21833   /* Calculate which registers need to be saved & save area size.  */
22621    determined by the presence of (use (unspec ... UNSPEC_TOC)), which
22952 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
23398      "exit" variants of the restore routines, which will reset the
24090       /* Peek at instruction to which this function returns.  If it's
24123 	 Move the note to a dummy blockage insn, which describes that
24179 	 those CR fields, which prevents any such instruction from being
24274      for which it was done previously.  */
24383 	       instruction, which we always want.  In particular we don't
24392   /* VRSAVE is a bit vector representing which AltiVec registers
24393      are used.  The OS uses this to determine which vector
24866 	 stack slot (which is not likely to be our caller.)
25031 		   lvx instruction, which we always want.  In particular
25237 		   lvx instruction, which we always want.  In particular
25963    After the addition, emit code to jump to FUNCTION, which is a
26751   /* Non-standard profiling for kernels, which just saves LR then calls
26790 	 from r0, which is where the prologue puts it.  */
26922    load or store and an integer insn which are executed in the same cycle.
26923    Branches have their own dispatch slot which does not count against the
27012                the mtctr instruction, which has the latency associated
27473   /* On machines (like the 750) which have asymmetric integer units,
27911              load/store instructions which make use of the LSU and which
28077    which INSN belongs). This means that INSN will be the last insn in the
28082    precedes the group to which INSN belongs).  This means that INSN will be
28569    'pad_goups' which tries to force the scheduler's grouping on the processor).
28585    - only the last issue slot, which is the branch slot, is vacant, but the next
28588      which means that a cracked insn (which occupies two issue slots) can't be
28667    any dispatch groups which have vacant issue slots, in order to force the
30375    are placeholders which no longer have any use.
31077      a different expression: fma(-m1, m2, a), which is the same
31523   unsigned int i, j, elt, which;
31534   for (i = which = 0; i < 16; ++i)
31538       which |= (elt < 16 ? 1 : 2);
31543   switch (which)
32270      integer modes of precision 2 * BITS_PER_WORD, which matches TImode
34128    stvx2dx instructions, which invert the order of doublewords in
34159    There are some operations sensitive to element order for which we
34161    These include CONST_VECTORs, for which we must swap the first and
34162    second halves of the constant vector; and SUBREGs, for which we
34165    which we should adjust the selected lane of the input.  We should
34175    load/store (which effectively removes the swap).  */
34215    Another form of permute is an UNSPEC_VPERM, in which the mask is
34217    that we can discover with ud-chains, in which case the above
34219    mask to be produced by an UNSPEC_LVSL, in which case the mask
34251   /* Set if this insn does not perform a vector operation for which
34438 	 it represents a vector splat for which we can do special
34569    having vector doublewords swapped in memory (in which case
34571    if vector doublewords are swapped in memory (in which case
34583      UNSPEC_LVE, UNSPEC_LVX, and UNSPEC_STVX, which have a PARALLEL
34584      body instead of a SET; and UNSPEC_STVE, which has an UNSPEC
34979 /* Find the insn from the Ith table entry, which is known to be a
35257   /* For each load and store in an optimizable web (which implies