config/rs6000/rs6000.c

749 /* COSTS_N_INSNS (1) ~ one add.  */
1842   /* The GPRs can hold any mode, but values bigger than one register
1879   /* ...but GPRs can hold SIMD data on the SPE in one register.  */
5385    depends on STEP and COPIES, one of which will be 1.  If COPIES > 1,
5387    vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5672   /* One field is non-constant and the other one is a constant.  Load the
5866      vectors, and convert these vectors to single precision, or do one
5939   /* Construct the vector in memory one field at a time
6120   /* Note that when we only have two 0->1 and 1->0 transitions, one of the
6121      masks will be all 1's.  We are guaranteed more than one transition.  */
6426 /* Given an address, return a constant offset term if one exists.  */
6490     /* For lo_sum addresses, we must allow any offset except one that
6902 	 code analogous to one in rs6000_legitimize_reload_address for
6924    to be legitimate.  If we find one, return the new, valid address.
6925    This is used from only one place: `memory_address' in explow.c.
6939    possibility of bit 16 being a one.
7434 	 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8917 	     this is a symbol plus a constant we can add in one insn,
9331 /* Return TRUE if a call to function FNDECL may be one that
10358   /* Optimize the simple case where the arg fits in one gpr, except in
10489    so we can pass the FP value just in one register.  emit_library_function
10759    PARALLEL, perhaps using more than one register type, this function
11337   /* The correct type is an array type of one element.  */
14006      _lower_.  We use one compare, but look in different bits of the
14164    SUBTARGET may be used as the target for computing one of EXP's operands.
16053      memset is about 4 instructions, so allow for one instruction to
16095 		 rather than waiting for reload.  This way we get one
16096 		 reload, not one per store.  */
16245 		 rather than waiting for reload.  This way we get one
16246 		 reload, not one per load and/or store.  */
16351      is assigned to one of the output registers.  */
16466    significant 0's, then one or more 1's, then zero or more 0's.  */
16482       /* Find the least significant one bit.  */
16518       /* Find the least significant one bit.  */
17059      look at cases where we don't need any extra registers, and one or more
18595       /* Add one for shift count in rlinm for scc.  */
18683       /* Similar, but add one for shift count in rlinm for scc and pass
18803 	 expression.  The expression may have one or both operands
18804 	 negated (if one, only the first one).  For condition register
19449        ordering compare that can be shared with this one.  */
20261      can't be generated if we care about that.  It's safe if one side
21051    multi-register moves.  It will emit at most one instruction for
21856      so we opt to save the GPRs in 64-bits always if but one register
22836 	 it exceeds SIZE.  If only one probe is needed, this will not
23235        prefix doesn't work.  (We only use one of the save routines at
23518       /* If it's just a single one, use mfcrf.  */
23847   /* Do any required saving of fpr's.  If only one or two to save, do
24165       /* Saving CR requires a two-instruction sequence: one instruction
24176 	 This means if any intervening instruction were to clobber one of
24848      give us one anyway.  */
24979 	      /* Of r11 and r12, select the one not clobbered by an
25683      it looks like we might want one, insert a NOP.  */
25869 		      /* If only one bit will fit, don't or in this entry.  */
25910       /* Only emit this long if there was at least one parameter.  */
25958    contains a pointer, and is the one used to pass the `this' pointer
26484 	 entirely within `low' and can be stored in one TOC entry.  */
26650 	  /* Write two quotes to get one.  */
26685   /* Now close the string if we have written one.  Then end the line.  */
27474      where one integer unit can do multiply and divides and the other
27880      and skews the ready list one way or the other to increase the likelihood
27932       /* If the pendulum is balanced, or there is only one instruction on
28436    one of the following schemes, depending on the value of the flag
28582    each insn.  A subsequent insn will start a new group if one of the following
28819 /* Sets the global scheduling context to the one pointed to by _SC.  */
30236    We want to go into the TOC section so at least one .toc will be emitted.
30237    Also, in order to output proper .bs/.es pairs, we need at least one static
30753 	 NEG or PLUS already counted so only add one.  */
30844    CLASS1 to one of CLASS2.  */
30882 	/* A move will cost one instruction per GPR moved.  */
30892   /* Moving between two similar registers is just one instruction.  */
31099   rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
31116   one = rs6000_load_constant_and_splat (mode, dconst1);
31129     rs6000_emit_nmsub (e0, d, x0, one);
33095 /* Hook to determine if one function can safely inline another.  */
33600   /* For canonical RTL, if only one arm is inverted it is the first.  */
34206    This seems promising at first, since we are just replacing one mask
34477 	   sum-across instructions define one operand with a specific
34778 /* OP is either a CONST_VECTOR or an expression containing one.
34837 /* Convert the non-permuting load INSN to a permuting one.  */
34863 /* Convert the non-permuting store INSN to a permuting one.  */
34961       /* Convert a non-permuting load to a permuting one.  */
34965       /* Convert a non-permuting store to a permuting one.  */