Lines Matching defs:as
8 under the terms of the GNU General Public License as published
1368 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1642 where tmp itself acts as an anchor, and can be shared between
1792 SCmode so as to pass the value correctly in a pair of
2651 /* Precalculate the valid memory formats as well as the vector information,
3316 request as an implicit --cpu. */
3683 the atomic versions as well, unless they explicity told us not to use quad
3724 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
3853 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4578 /* 32-bit vectors loaded into registers are stored as double
4770 /* Libmass is suitable for unsafe math only as it does not correctly support
4771 parts of IEEE with the required precision such as denormals. Only support
5362 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5365 the corresponding "float" is interpreted as an SImode integer. */
5479 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5621 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5865 precision is actually represented as a double, and either make 2 V2DF
6315 SPE, so using a vector or float variable directly as an operand is
6896 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6898 recognizes some LO_SUM addresses as valid although this
6927 OLDX is the address as it was before break_out_memory_refs was
6986 worst-case. The mode here is just a hint as to the registers
7961 addr_space_t as ATTRIBUTE_UNUSED)
7988 been rejected as illegitimate. */
8144 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
8179 /* Output insns to set DEST equal to the constant SOURCE as a series of
8239 Output insns to set DEST equal to the constant C as a series of
8519 registers as temporaries. We must make sure this is acceptable. */
8578 as two parts. However, this premature splitting is a problem when DFmode
8601 p1:SD) if p1 is not of floating point class and p0 is spilled as
8655 p:DD)) if p0 is not of floating point class and p1 is spilled as
9056 /* Use V4SImode as representative of all 128-bit vector types. */
9190 /* Note that we do not accept complex types at the top level as
9225 memory, just as large structures are always returned. TYPE will be
9235 registers as it would if it were the first and only function
9268 /* Do a trial code generation as if this were going to be passed
9269 as an argument; if any part goes in memory, we return NULL. */
9462 /* The mode the ABI uses for a word. This is not the same as word_mode
9471 /* On rs6000, function arguments are promoted, as are function return
9517 /* GCC used to pass structures of the same size as integer types as
9559 testing the mode size is a boneheaded way to do this as it means
9560 that other types such as complex int are also double word aligned.
9625 implement the "aggregate type" check as a BLKmode check here; this
9926 treated as if consisting entirely of ints.
9937 sizeof(type)/8, but this is wrong in a case such as
9988 as complex int due to a historical mistake. */
9996 So are other 2 word items such as complex int due to
10291 else goes in int registers, packed as in memory.
10473 TYPE is the data type of the argument (as a tree).
10642 as complex int due to a historical mistake. */
10707 passed in the last FPR as well.
10781 (gprs or memory) as well as VRs, we do not use the partial
10783 PARALLEL including a memory element as necessary. */
10804 (gprs or memory) as well as FPRs, we do not use the partial
10806 PARALLEL including a memory element as necessary. */
10953 /* Find mode as it is passed by the ABI. */
11115 CUM is as above.
11586 As are any other 2 gpr item such as complex int due to a
11673 temporary. (This is the same code as used for SPARC.) */
11726 function as not reading global memory, but it can have arbitrary side
12438 /* Return a constant vector for use as a little-endian permute control vector
12842 SPR number and SPR regno as the last two operands. */
12850 CR as the last operand. */
12959 would be incorrect as many of the CODE_FOR values could be
13288 /* If we have a vector compromised of a single element, such as V1TImode, do
14010 bits are set as follows:
14164 SUBTARGET may be used as the target for computing one of EXP's operands.
14403 /* We use V1TI mode as a special container to hold __int128_t items that
14622 /* AIX libm provides clog as __clog. */
15528 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
15557 arguments, and it is returned as a decl for the vectorizer (such as
17344 says the address is good (as otherwise the entire address
17388 says the address is good (as otherwise the entire address
17981 register from BASE_REGS is needed as an intermediate
18806 CR codes as NOTs, but not handle NOTs of them. */
19187 without this hack would be output as "x@toc+4". We
19264 without this hack would be output as "x@toc+8@l(9)". We
19388 /* Functions need to have their entry point symbol visibility set as
19389 well as their descriptor symbol visibility. */
19454 /* If we have an unsigned compare, make sure we don't have a signed value as
19638 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
19725 can be used as that dest register. Return the dest register. */
19907 /* Maybe we have a guess as to how likely the branch is. */
19916 cpus as static prediction overrides processor dynamic
19917 prediction. For older cpus we may as well always hint, but
19918 assume not taken for branches that are very close to 50% as a
20024 /* See if the comparison works as is. */
20162 /* Swap operands if we can, and fall back to doing the operation as
20404 /* Same as above, but for ints (isel). */
20507 COND is true. Mark the jump as unlikely to be taken. */
20671 do not want any of the existing MEM_ATTR data, as we're now
21345 /* Stack frame remains as is unless we are in AltiVec ABI. */
21452 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
22430 /* regs_ever_live has LR marked as used if any sibcalls are present,
22444 this as a store. */
22726 /* Emit the correct code for allocating stack space, as insns.
22728 The generated code may use hard register 0 as a temporary. */
22846 /* Otherwise, do the same as above, but in a loop. Note that we must be
23412 /* Return the register number used as a pointer by out-of-line
23425 or jump_insn as appropriate. */
23534 as well, using logical operations to combine the values. */
23547 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
23561 /* Emit function prologue as insns. */
23724 /* CR register traditionally saved as CR2. */
23887 /* Save GPRs. This is done as a PARALLEL if we are using
24121 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
24178 this from happening, we mark the store to memory as a use of
24409 be using r12 as frame_reg_rtx and r11 as the static chain
24803 /* Emit function epilogue as insns. */
24895 /* CR register traditionally saved as CR2. */
25370 /* Restore GPRs. This is done as a PARALLEL if we are using
25507 is why it is a bad idea to emit the cfa_restores as a group
25760 (as defined in sys/debug.h). Thus we can not use the .tbtab
25815 set up as a frame pointer, even when there is no alloca call. */
25887 an 8 byte struct counts as 2; and thus the maximum value is 8. */
25952 multiple inheritance. The thunk acts as a wrapper around a virtual
25968 The effect must be as if FUNCTION had been called directly with the
26064 There's not really enough bulk here to make other passes such as
26096 AIX TOC 2 crt0 as Y option option
26211 instead, there should be some programmatic way of inquiring as
26694 SECTION_DESC can be any string, as long as it is different for each
26697 We name the section in the same manner as xlc. The name begins with an
26753 the function prologue as little as possible as it isn't easy to
27073 by a fixed point operation is used as the address
28438 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
28568 estimated processor grouping on the compiler (as opposed to the function
28580 The function estimates the group boundaries that the processor will form as
28732 /* We're beginning a new block. Initialize data structures as necessary. */
28935 identifier as an argument, so the front end shouldn't look it up. */
28944 arguments as follows:
29069 /* AltiVec defines four built-in scalar types that serve as vector
29087 /* Mangle IBM extended float long double as `g' (__float128) on
29099 /* Handle a "longcall" or "shortcall" attribute; arguments as in
29168 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
29385 r0 is special and we must not select it as an address
29584 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
29585 instruction will reach 'foo', otherwise link as 'bl L42'".
29681 zero, otherwise we allocate register(s) as necessary. */
29704 /* Use a different reg for the intermediate value, as
30182 However, if this is being placed in the TOC it must be output as a
30302 that does not behave as expected by the middle-end. */
30378 all aliases as alternative labels in front of the definition. */
30441 all aliases as alternative labels in front of the definition. */
30831 addr_space_t as, bool speed)
30833 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
31194 /* Load up the constant 1.5 either as a scalar, or as a vector. */
31360 serve as the permute control vector. Then, in BE mode,
31374 That is, the leftmost 4 bytes of vr10 are interpreted as the
31898 /* Return an rtx describing a return value of MODE as a PARALLEL
31948 /* Do a trial code generation as if this were going to be passed as
32269 same ABI as for -m32. But default_scalar_mode_supported_p allows
32673 /* Print out the target options as a list for -mdebug=target. */
32757 /* If the function changed the optimization levels as well as setting target
33394 as uses in CALL_INSN_FUNCTION_USAGE. */
33721 exactly the same as the output registers, or there is no overlap.
34142 so long as the correct memory order is preserved. If we have
34173 call to vec_vsx_{ld,st}.) We can handle these as well, but rather
34199 M with M' as follows:
34211 remove as a result of this transformation to determine if it's
34221 generate several instructions to compute M' as above at run time,
34436 /* Opportunity: If XEXP (op, 0) has the same mode as the result,
34471 problematic, as both the permute control vector and the ordering
34476 as are vector select and concatenate operations. Vector
34611 /* A convert to single precision can be left as is provided that
34650 register swap must have only permuting loads as reaching defs.
34652 register swaps or permuting stores as reached uses. */
34729 as there is a possibility of a swap being reached from multiple
35099 both DImode. We must recognize this and treat it as a