config/mips/mips.c

134    instructions for o32, for which the stack alignment is 8 bytes.)
268      of this instruction is the result of the comparison, which has mode
1984 	 R_MIPS_GOT16 relocation.  We must correctly predict which of
2217 	 relocation.  Use mips_split_p to determine which.  32-bit
2321      hard frame pointer, both of which are usually valid base registers.
2383      for o64, which has historically only guaranteed 64-bit alignment
2528    for LW and SW, and so on.  An exception is LWSP and SWSP, which have
2898    instruction itself (which is not necessarily the last instruction
2972 /* If OP is an UNSPEC address, return the address to which it refers,
3018    for which $gp itself is not a valid base register or addition operand.  */
3557    a LO_SUM.  CONTEXT is the context in which X appears.  */
3568 	 guarantee about which symbolic constants are acceptable as asm operands
3569 	 versus which must be forced into a GPR.  */
3594    relocations.  CONTEXT is the context in which *LOC appears.  */
4147       /* If it's an add + mult (which is equivalent to shift left) and
4523    SPLIT_TYPE is the condition under which moves should be split.  */
4615 	 which order to do them.  */
5366 	 say, which is OK because they are not covered by the standard ABI.  */
5617      either the o32 or the o64 ABI, both of which pass at most 2 arguments
5772    list them in FIELDS (which should have two elements).  Return 0
6121 	 Two pointers are to the overflow area, which starts at the CFA.
6130 	 We also keep two one-byte offsets, which are to be subtracted
6223       /* Emit code to initialize OVFL, which points to the next varargs
6710 /* A chained list of functions for which mips16_build_call_stub has already
6795    general registers.  FP_CODE is the code describing which arguments
6836    for functions which take arguments in the floating-point registers.
6917      function, it will associate the symbol with the stub (which,
7266      stub which does not expect one, then we're in trouble.  We can't
7269      which stub to use for the various calls in this object file.
7281   /* If we are calling a stub which handles a floating-point return
7677 /* Expand a movmemsi instruction, which copies LENGTH bytes from
8218 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8858    adjustment.  So, we do the adjustment here.  The arg pointer (which
8860    pointer (which may be eliminated) points to the stack pointer after
8981      64-bit registers which means that dwarf information cannot be precise
9292      such as GDB.  Do the same for o64, which is sometimes used with
9443 /* Return the index of the lowest X in the range [0, SIZE) for which
9627 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9645    registers in the memory immediately below *OFFSET_PTR, which is a
9858   /* Save or restore registers in the range $s2...$s8, which
9935    One example of this (and one which needs several checks) is that
9956       /* FUNCTION_PROFILER includes a JAL to _mcount, which again
10056    the usual case in which all branches are short.
10281 	 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10429   /* Find out which GPRs we need to save.  */
10464   /* Find out which FPRs we need to save.  This loop must iterate over
10712      predict which applies to a given function, so let's keep things
10731    LOAD_P says which.  */
11217   /* Tell the assembler which register we're using as the global
11867    says which.  */
11898   /* Work out which register holds the frame address.  */
12483   /* Handle cases in which only one class deviates from the ideal.  */
12543    copying between one of the registers in RCLASS and value X, which
12890 /* Return the assembly code for INSN, which has the operands given by
12891    OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12973 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13306 /* Output and/or return the asm template for sync loop INSN, which has
13334    which has the operands given by OPERANDS.  */
13347 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
13392 	       miss (both primary and secondary) and the line which is
13531    which causes the default routine to abort.  We just return false
13831 /* A TUNE_MACC_CHAINS helper function.  Search ready queue READY, which
13892    in which INSN1 and INSN2 can probably issue in parallel, but for
13893    which (INSN2, INSN1) should be less sensitive to instruction
14258 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
14264 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
14319 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
14882    HAS_TARGET_P says which.  EXP is the CALL_EXPR that calls the function
14908    function; TYPE says which.  EXP is the CALL_EXPR that calls the
15382    virtual_incoming_args_rtx (which should never occur in X otherwise).  */
15561 /* A note_stores callback for which DATA points to an instruction pointer.
15698 		     clear which position is better performance-wise,
15961      LAST_SET[X].TIME is the time at which that instruction was issued.
16213    Prefer MULT -- which is shorter -- in the event of a tie.  */
16281    (which is usually the "rt" field).
16480 /* Look up symbolic constant X in HTAB, which is a hash table of
16551       /* Check for local %gots (and %got_pages, which is redundant but OK).  */
16947   /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF.  Also during
17060   /* Find out which register contains the "this" pointer.  */
17153    which is either MASK_MIPS16 or MASK_MICROMIPS.  */
17427 	       "which specify a %s processor",
17553   /* Decide which rtx_costs structure to use.  */
17772      ILP32 mode, which is selected by -mlong32.  The problem is that the
17906 /* Swap the register information for registers I and I + 1, which
18278    register into (from) which the contents of MEM1 will be loaded
18322    in an LWP or SWP instruction; LOAD_P says which.  */
18353 /* Return the assembly instruction for a microMIPS LWP or SWP in which
18671      setting should be irrelevant.  The question then is: which setting
18944   int i, nelt, which;
18959   for (i = which = 0; i < nelt; ++i)
18963       which |= (ei < nelt ? 1 : 2);
18968   switch (which)
18994   /* If we were given a two-vector permutation which just happened to
19001   if (!ok && which == 3)
19020   unsigned int i, nelt, which;
19029   for (i = which = 0; i < nelt; ++i)
19033       which |= (e < nelt ? 1 : 2);
19037   if (which == 2)
19042   d.one_vector_p = (which != 3);