config/mep/mep.c

12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
401     error ("only one of -ms and -mm may be given");
403     error ("only one of -ms and -ml may be given");
405     error ("only one of -mm and -ml may be given");
407     error ("only one of -ms and -mtiny= may be given");
409     error ("only one of -mm and -mtiny= may be given");
418 	error ("-mc= must be -mc=tiny, -mc=near, or -mc=far");
708    be deleted by a peephole2 if SRC3 is already in $lo.  */
731    This function is intended to be used by the peephole2 pass.  Since
816 /* Return true if SET can be turned into a post-modify load or store
817    that adds OFFSET to GPR.  In other words, return true if SET can be
832   /* Only simple SETs can be converted.  */
836   /* Point REG to what we hope will be the register side of the set and
837      MEM to what we hope will be the memory side.  */
901    new pattern in INSN1; INSN2 will be deleted by the caller.  */
926    be persuaded to do SET_INSN as a side-effect.  Return true if so.  */
1115 /* Be careful not to use macros that need to be compiled one way for
1525 /* Cases where the pattern can't be made to use at all.  */
1546      be split by mep_emit_mov anyway.  */
1557     /* These are supposed to be generated with adds of the appropriate
1559        be accessed as normal symbols because adding a dependency on
1643       /* The high part of CR <- GPR moves must be done after the low part.  */
2052      coprocessor might be done directly or through memory,
2184    can be moved directly into registers 0 to 7, but not into the rest.
2464   /* Additional registers that need to be saved for IVC2.  */
2487 	/* We need these to have stack slots so that they can be set during
2503      mark it used in the epilogue if it needs to be saved and restored.
2505      clobber $11.  This case has to be handled specially both here and in
2768 	   ALLOCATE_INITIAL_VALUE.  The moves emitted here can then be safely
2780 	    int be = TARGET_BIG_ENDIAN ? 4 : 0;
2784 					      sp_offset - rss + be));
2806 					      sp_offset - rss + (4-be)));
3036       /* Restore this one last so we know it will be in the temp
3793 /* This isn't as optimal as it could be, because we don't know what
4594 		      "variable %D of type %<io%> must be uninitialized", decl);
4599 		      "variable %D of type %<cb%> must be uninitialized", decl);
4701    the section; 0 if the default should be used.
4875   /* Set's source should be read-only.  */
5065 	    /* Other insns that should not be in the last two opcodes.  */
5235   /* The initial counter value.  This is known to be a general register.  */
5251      jump instruction, it has to allow the counter to be stored anywhere
5271      so that the first one is the most likely to be X in case (2) above.  */
5276 /* Return true if LOOP can be converted into repeat/repeat_end form
5285   /* There must be exactly one doloop_begin and at least one doloop_end.  */
5578 		       But we must be careful to put the erepeat
5596 		/* Generate a label to be used by the erepat insn.  */
5764   /* The first insn should be $sp = $sp + N */
6133       /* CONST_INTs can only be bound to integer operands.  */
6183 /* Report that ARG cannot be passed to argument ARGNUM of intrinsic
6203 	    error ("argument %d of %qE must be in the range %d...%d",
6206 	    error ("argument %d of %qE must be a multiple of %d",
6235      intrinsics may only be available in VLIW mode, or only in normal mode.  */
6282 	      error ("argument %d of %qE must be an address", a+1, fnname);
6320 	  error ("argument %d of %qE must be in the range %d...%d",
6472    In practice, instruction selection will be a bear.  Consider in
6507 	 so any pair of mep_mulr()s will be inter-dependent.   We should
6812    instruction COP.  COP always satisfies INSN_P, but CORE can be
6850      have their own location because there can be no assembler labels
6904 /* Mark coprocessor instructions that can be bundled together with
6929   /* Note: this doesn't appear to be true for JUMP_INSNs.  */
6990       /* If we're not optimizing enough, there won't be scheduling
7005 	     and allows a COP insn to be first.  */
7132    be synthesized.  OPERANDS[1] is a register_operand.  For sign
7133    and zero extensions, it may be smaller than SImode.  */
7145    can be a general_operand.