config/m32c/m32c.c

8    under the terms of the GNU General Public License as published
141    be easily enabled individually, by replacing the '0' with '1' as
429    registers, as there are a limited number of true registers and the
625    function that way, leaving QImode as the only unique case.  */
778    r0 or r1, as those are the only real QImode registers.  CR regs get
875 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
1053    width as well, for example, r0l, r0, and r2r0 would each have
1095 	 |        through r0 as needed
1342    pushed).  The first few real arguments may be in registers as
1474 /* HImode and PSImode are the two "native" modes as far as GCC is
1714      doesn't work as cleanly as this code implies, so until we've had
1862    worry about is frame base offsets, as $fb has a limited
2006 				      bool strict, addr_space_t as)
2008   if (as == ADDR_SPACE_FAR)
2084   else if (as != ADDR_SPACE_GENERIC)
2095 				    addr_space_t as)
2097   if (as != ADDR_SPACE_GENERIC)
2146       /* This is unpredictable, as we're truncating off usable address
2329 		   addr_space_t as ATTRIBUTE_UNUSED,
2604       /* We can't actually represent this as an rtx.  Do it here.  */
2746 			  /* Integers used as addresses are unsigned.  */
3122       /* We never output these as global.  */
3297   /* Push/pop get done as smaller push/pops.  */
3395    POP.L as we can only *push* SImode.  */
3880   rtx temp1; /* b as SI */
3881   rtx scale /* i as SI */;
3882   rtx temp2; /* a*b as SI */
4107 /* Mark all the subexpressions of the PARALLEL rtx PAR as
4193    interrupts, we must manually unwind the frame as the REIT opcode
4546    stack pointer doesn't have as flexible addressing as the frame