config/i386/i386.c

4360   /* Only one of them can be active.  */
5109 /* Hook to determine if one function can safely inline another.  */
5536      differences in the return value ABI.  Note that it is ok for one
5729    these builtins were declared with, and replace it with one of the two
6746   /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6753   /* Rule #3: If one of the classes is MEMORY, the result is MEMORY.  */
6757   /* Rule #4: If one of the classes is INTEGER, the result is INTEGER.  */
6765   /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6950 	  /* When size > 16 bytes, if the first one isn't
6965 	  /* If one class is MEMORY, everything should be passed in
6976 	      /* The first one should never be X86_64_SSEUP_CLASS.  */
6988 	      /* The first one should never be X86_64_X87UP_CLASS.  */
8677   /* The correct type is an array type of one element.  */
9681      with one instruction.  */
9838 	 as one instruction).  */
10090 /* Return the offset between two registers, one to be eliminated, and the other
10194 	 to save as it is cheap to use one or two push instructions but very
10781   /* Prefer the one specified at command line. */
10999 	 values of N from 1 until it exceeds SIZE.  If only one probe is
11176 	 it exceeds SIZE.  If only one probe is needed, this will not
11618 	 the stack frame saving one cycle of the prologue.  However, avoid
12160   /* If we're only restoring one register and sp is not valid then
12446      it looks like we might want one, insert a NOP.  */
13553 	 lead to spill failures when the register is one word out
14531    to be legitimate.  If we find one, return the new, valid address.
14532    This macro is used in only one place: `memory_address' in explow.c.
16285   /* Use one byte shorter RIP relative addressing for 64bit mode.  */
16518 /* Split one or more double-mode RTL references into pairs of half-mode
16569 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16578 /* Set to 1 for compatibility with brain-damaged assemblers.  No-one
16580    with gcc.  No-one wants to fix gcc because that causes
17172 /* Generate one or more insns to set ENTITY to MODE.  */
17174 /* Generate one or more insns to set ENTITY to MODE.  HARD_REG_LIVE
17240    have the values zero or one, indicates the ffreep insn's operand
17954 		 of one.  A rumor has it that Intel recommends two movsd
17957 		 still be one, I'm not sure why this would be better.  */
18167    memory references (one output, two input) in a single insn.  */
18326    memory references (one output, one input) in a single insn.  */
18458       /* Need a new scratch register since the old one has result
18851      agu dependence, the one with short distance takes effect.  */
19299   /* If one of operands is memory, source and destination must match.  */
20645 	   avoid two branches.  This costs one extra insn, so disable when
21106 		 to trapping one), however on i386 we currently emit all
21262 		     condition to trapping one), however on i386 we currently
21337       /* If one of the two operands is an interesting constant, load a
22066   /* Allow the comparison to be done in one mode, but the movcc to
22285 	  /* Add one to the odd shuffle indicies:
22342 	  /* By combining the two 128-bit input vectors into one 256-bit
22557 	  /* Without SSE4.1, we don't have V2DImode EQ.  Perform one
23101 	 Do an lea to the last part and use only one colliding move.  */
23349 	 pentium4 a bit; no one else seems to care much either way.  */
24610 /* This function is like the previous one, except here we know how many bytes
24987    and alignment, but always has one of the following overall structures:
25210      main loop and epilogue (ie one load of the big constant in the
25606   /* This formula yields a nonzero result iff one of the bytes is zero.
25702          often used and I use one fewer register for the lifetime of
25909      circumstances.  Determine if we have one of those.  */
26043    Includes addr32 prefix, does not include the one-byte modrm, opcode,
26501       /* Floating point stores require value to be ready one cycle earlier.  */
26513       /* There is one cycle extra latency between an FP op and a store.  */
26529 	  /* Claim moves to take one cycle, as core can issue one load
26558 	  /* Claim moves to take one cycle, as core can issue one load
27083    if at least one dependence was added or NULL otherwise.  */
27210 	       region contains more than one block.  */
27295    one cycle.  */
27706      TODO: Probably one should optimize for size only when var is not escaping.  */
30865 	 with another one. E.g.: OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL
34957   /* At least one more version other than the default.  */
35004      could still be ambiguity.  If more than one function version is suitable
35005      to execute,  which one should be dispatched?  In future, allow the user
35177   /* At least one function decl should have the target attribute specified.  */
35181   /* Diagnose missing target attribute if one of the decls is already
35496 	 is comdat to keep just one copy.  */
35610   /* The last field is an array of unsigned integers of size one.  */
36088    where we expect a vector.  To avoid crashing, use one of the vector
36328 	  /* If we aren't optimizing, only allow one memory operand to be
37748 	  /* If we aren't optimizing, only allow one memory operand to
38465 	     and if the special builtin is one that requires strict
38521 		 and if the special builtin is one that requires strict
38733    SUBTARGET may be used as the target for computing one of EXP's operands.
41469   /* Make sure success has a non-zero value by adding one.  */
41521   /* Make sure success has a non-zero value by adding one.  */
41777    The macro can't work reliably when one of the CLASSES is class containing
42044    one in class CLASS2.
42457 		     shift with one insn set the cost to prefer paddb.  */
43016 		   "argument to %qE attribute is neither zero, nor one",
43189   /* For 32-bit, everything's fine if we have one free register.  */
43804 	      /* Two NOPs count as one instruction.  */
44406       /* There's no way to set one QImode entry easily.  Combine
44967   /* Values where only one field is non-constant are best loaded from
45864 	     So if we need one, follow the store with a load.  */
46226      one.  */
46432    of bits of the mantissa of MODE, which must be one of DFmode or SFmode.  */
46569   rtx xa, TWO52, tmp, one, res, mask;
46593   one = force_reg (mode,
46600                           gen_rtx_AND (mode, one, tmp)));
46633   rtx xa, xi, TWO52, tmp, one, res, mask;
46655   one = force_reg (mode, const_double_from_real_value (dconst1, mode));
46660                           gen_rtx_AND (mode, one, tmp)));
46697   rtx xa, xa2, dxa, TWO52, tmp, half, mhalf, one, res, mask;
46722   one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
46723   mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
46731                           gen_rtx_AND (mode, one, tmp)));
46736                           gen_rtx_AND (mode, one, tmp)));
46799   rtx xa, mask, TWO52, one, res, smask, tmp;
46833   one = force_reg (mode, const_double_from_real_value (dconst1, mode));
46838                           gen_rtx_AND (mode, mask, one)));
47824   /* Try one of the AVX vpermil variable permutations.  */
47887    when all of the elements in PERM fit within one vector and we merely
47977   /* For AVX2, test whether we can permute the result in one instruction.  */
48051      respective lanes only when these elements are all in one
48062   /* First we apply one operand permutation to the part where
48132 	 3 insn sequence.  While that is one insn longer,
48569       /* For one operand, the only useful vperm2f128 permutation is 0x01
48836 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
49110    with two "shifts", two "truncs" and one "concat" insns for "odd"
49111    and two "truncs" and one concat insn for "even."
49422       /* These can be implemented via interleave.  We save one insn by
49491    will 2 vpermi2w, 2 vpshufb and one vpor instruction.  */
49519   /* Prepare permutations such that the first one takes care of
49520      putting the even bytes into the right positions or one higher
49521      positions (ds[0]) and the second one takes care of
49522      putting the odd bytes into the right positions or one below
49761 /* If a permutation only uses one operand, make it clear. Returns true
50010   /* Note that for AVX this isn't one instruction.  */
50116 	 Happily, that is even one insn shorter than even extraction.
51388      Window number one is full, if window zero's bytes plus window
51389      one's bytes is 32, or if the bytes of the new instruction added
51844       /* If the function isn't exported, we can pick up just one ISA