Lines Matching defs:which
623 for a particular anchor is -4088 + 1 + 4095 bytes, which is
751 /* The maximum number of insns skipped which
760 /* The processor for which instructions should be scheduled. */
776 /* The bits in this mask specify which
780 /* The bits in this mask specify which instruction scheduling options should
861 problems in GLD which doesn't understand that armv5t code is
2359 which are faster. */
2735 with the default CPU, but which also supports the command
2809 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
2894 for a particular anchor is 248 + 1 + 4095 bytes, which is
3038 which keeps r9 available. The EABI specifies r9 as the PIC register. */
3137 calculation, which is 2 instructions. */
3594 prologue, which we can test by looking at the offsets. */
3758 MODE is the mode in which the operation is being performed;
4063 /* As above, but extra parameter GENERATE which, if clear, suppresses
4085 /* Find out which operations are safe for a given CODE. Also do a quick
4436 x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
4472 x = y | constant (which has set_zero_bit_copies number of trailing ones).
4984 hard-float ABI on a CPU which doesn't support single-precision
5087 We don't care about which register here, so we can short-cut
5107 memory (unless they're over 16 bytes, which will break since
5132 ARM and Thumb compilers, which always return aggregates in memory. */
5151 /* Find the first field, ignoring non FIELD_DECL things which will
5876 anonymous argument which is on the stack. */
6052 or a hard register in which to store the argument.
6058 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6064 other arguments are passed on the stack. If (NAMED == 0) (which happens
6351 are compatible, and 2 if they are nearly compatible (which causes a
6466 /* For "f", be conservative, and only cater for cases in which the
6776 function but which are not used. Hence we could miss an opportunity
7852 with absolute addresses which often allows for the base register to
8007 /* Without ldrd, we use stm/ldm, which does not
8015 of which the (reg+high) gets turned into a reload add insn,
8028 which post-reload CSE can simplify in most cases to eliminate the
8081 -8, -4, and 4, which we try to produce here. */
8216 patterns), nice doubles and symbol_refs which refer to the function's
9039 /* For the targets which have a very small and high-latency multiply
9492 X, which is contained with an operation with code OUTER_CODE.
9531 unless we don't have HW FP, in which case everything
9596 (ldm_1st) which will load the number of registers mentioned in
10719 this is just the control part which has no additional
12074 close to a conditional branch which depends on them, so that we can
12238 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
12257 which is always 1. */
12298 /* Recognize immediates which can be used in various Neon instructions. Legal
12756 {0, C, 0, C, 0, C, 0, C} which can be loaded using
12768 /* Generate code to load VALS, which is a PARALLEL containing only
13042 /* Return TRUE if OP is a memory operand which we can load or store a vector
13195 /* Values which must be returned in the most-significant end of the return
13643 We cheat here and test 'arm_ld_sched' which we currently know to
13683 Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
13684 an array ORDER which describes the sequence to use when accessing the
14137 which are constructed from BASEMEM.
14429 unaligned copies on processors which support unaligned semantics for those
14746 subject to loop unrolling, which makes tuning this condition a little
15048 In all cases OP will be either EQ or NE, but we don't need to know which
15443 /* We have a pseudo which has been spilt onto the stack; there
15560 /* We have a pseudo which has been spilt onto the stack; there
15833 register and has no side effects, in which case it sets BASE and
16205 We fix this by performing a scan after scheduling, which notices
16206 which instructions need to have their operands fetched from the
16580 not take into account the size of the pool (which is still under
16643 its maximum address (which can happen if we have
16873 /* The instruction after which we will insert the jump. */
16876 /* The address at which the jump instruction will be placed. */
16985 /* Record INSN, which will need fixing up to load a value from the
16987 function; LOC is a pointer to the part of the insn which requires
16988 fixing; VALUE is the constant that must be loaded, which is of type
17240 /* Get the register with which we are comparing. */
17936 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
18658 possible, which allows use of appropriate alignment tags.
18912 /* Note that n is never zero here (which would give no output). */
19178 r13 is the stack pointer which is always preserved,
19213 which are call saved and which are used by this function. */
19258 /* Just look at cfg info, which is still close enough to correct at this
19281 /* Compute a bit mask of which registers need to be
19283 This is used by arm_get_frame_offsets, which may add extra registers. */
19297 IP (which will hold the old stack pointer), LR and the PC. */
19337 might be a double or long long which we will load/store using
19369 /* Compute a bit mask of which registers need to be
19402 /* Use thumb_find_work_register to choose which register
19423 /* This is the same as the code in thumb1_expand_prologue() which
19424 determines which register to use for stack decrement. */
19547 being saved. 1) a stack frame was created, in which case
20053 which STRD can be generated. */
20196 friendly to the stack unwinding code, which only wants to see a single
20307 SAVED_REGS_MASK shows which registers need to be restored.
20354 /* Now restore every reg, which may include PC. */
20425 each of which emits one pop_multi instruction. */
20651 /* Current register and next register form register pair for which
20863 offsets and in prologue/epilogue code. Also calculates which registers
20881 which causes get_insns to return the insns for the sequence,
20882 not the function, which will cause leaf_function_p to return
21243 /* Compute which register we will have to save onto the stack. */
21275 /* ??? The CFA changes here, which may cause GDB to conclude that it
21278 we've described the save of SP, which will override the default
21689 of further digits which we don't want to be part of the operand
22876 is the previous target label which is only used once, and the label this
22930 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
23357 which is the frame pointer
23466 number of components into which the copy has been decomposed. */
23780 /* Match registers to be popped with registers into which we pop them. */
23844 /* Work out which register currently contains the frame pointer. */
23884 any registers into which we can pop them, then we must move the return
24061 longest length, which in turn sets the far jump attribute to true.
24136 FOR_PROLOGUE indicates which we're generating. */
24155 instruction, which should make this a win even when optimizing
24209 /* The bits which aren't usefully expanded as rtl. */
24267 /* Oh dear! We have no low registers into which we can pop
24278 /* Find lo register(s) into which the high register(s) can
24320 structure was created which includes an adjusted stack
24741 function). So instead we look for a scratch register into which
24746 attempt to locate a call preserved register which is used by this
24989 /* saved_regs_mask should contain IP which contains old stack pointer
25382 register which is overwritten by the load. */
25680 will know which tag is being set.
25763 which don't support armv7ve. */
27395 /* Vectors which aren't in packed structures will not be less aligned than
28478 int i, nelt, which;
28489 for (i = which = 0; i < nelt; ++i)
28493 which |= (ei < nelt ? 1 : 2);
28497 switch (which)
28535 unsigned int i, nelt, which;
28544 for (i = which = 0; i < nelt; ++i)
28548 which |= (e < nelt ? 1 : 2);
28552 if (which == 2)
28557 d.one_vector_p = (which != 3);
28868 /* Returns true if the pattern is a valid symbolic address, which is either a
29303 to permit unaligned copies on processors which support unaligned