config/arm/arm.c

777    instructions we are allowed to generate.  */
2900   /* V5 code we generate is completely interworking capable, so we turn off
3201      generate additional returns.  */
4069 		  int generate)
4101 	  if (generate)
4113 	  if (generate)
4123 	  if (generate)
4132 	  if (generate)
4145 	  if (generate)
4153 	  if (generate)
4167 	  if (generate)
4175 	  if (generate)
4192       if (generate)
4207       if (generate)
4277 	      if (generate)
4294 	      if (generate)
4328 	      if (generate)
4343       /* See if we can generate this by setting the bottom (or the top)
4346 	 too much.  Be careful, however, not to generate this when the
4360 				 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
4363 					    source, subtargets, generate);
4365 		  if (generate)
4385 				 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
4388 					    source, subtargets, generate);
4390 		  if (generate)
4416 	      if (generate)
4443 	  we generate.
4449 	  if (generate)
4484 	  if (generate)
4515 	  if (generate)
4549 	      if (generate)
4564 	  if (generate)
4584 	      if (generate)
4601 	  if (generate)
4665   if (generate)
4713       if (generate)
6441    a call from the current function to DECL.  We generate a long_call
6448    However we do not generate a long call if the function:
7870 	  /* It'll most probably be more efficient to generate the base
12730    using VDUP, generate instructions to do so and return an RTX to
14197    Returns true iff we could generate a new instruction.  */
14261    Returns true iff we could generate a new instruction.  */
14317    Returns true iff we could generate a new instruction.  */
14964   /* If we cannot generate any LDRD/STRD, try to generate LDM/STM.  */
15051    generate this call.  */
15416 /* Generate a sequence of insns that will generate the correct return
15879    single LDRD/STRD instruction.  Returns true iff we can generate a
16032   /* Make sure we generate legal instructions.  */
16180    generate code to branch around it.
17008      to generate duff assembly code.  */
19651       /* See if we need to generate an extra instruction to
19827 	 function will be emitted as assembly immediately after we generate
20036   /* For dwarf info, we generate explicit stack update.  */
20141   /* Attach dwarf info to the first insn we generate.  */
20178   /* For the body of the insn we are going to generate an UNSPEC in
20197      stack decrement per instruction.  The RTL we generate for the note looks
20497   /* We cannot generate ldrd for PC.  Hence, reduce the count if PC is
20499      and we can generate pop with PC.  If num_regs is odd, it will be
20613       /* There are 2 registers to be popped.  So, generate the pattern
21253       /* Handle a word-aligned stack pointer.  We generate the following:
23632       /* Special case.  Do not generate a POP PC statement here, do it in
25071   /* Naked functions don't have epilogue.  Hence, generate return pattern, and
25176          any groupings made in the prologue and generate matching
28250 	   queue to generate this. Getting a vector mask with a