Lines Matching defs:AS
707 unsigned AS = getLoadStoreAddressSpace(C[0].Inst);
708 unsigned VecRegBytes = TTI.getLoadStoreVecRegBitWidth(AS) / 8;
768 F.getContext(), SizeBytes * 8, AS, Alignment, &VectorizedSpeed);
772 << AS << " with alignment " << Alignment.value()
778 (TTI).allowsMisalignedMemoryAccesses((F).getContext(), VecElemBits, AS,
783 << AS << " with alignment " << Alignment.value()
803 bool IsAllocaAccess = AS == DL.getAllocaAddrSpace() &&
829 !TTI.isLegalToVectorizeLoadChain(SizeBytes, Alignment, AS)) ||
831 !TTI.isLegalToVectorizeStoreChain(SizeBytes, Alignment, AS))) {
862 unsigned AS = getLoadStoreAddressSpace(C[0].Inst);
876 if (AS == DL.getAllocaAddrSpace()) {
1355 unsigned AS = Ptr->getType()->getPointerAddressSpace();
1356 unsigned VecRegSize = TTI.getLoadStoreVecRegBitWidth(AS);
1371 Ret[{getUnderlyingObject(Ptr), AS,
1384 unsigned AS = getLoadStoreAddressSpace(Instrs[0]);
1385 unsigned ASPtrBits = DL.getIndexSizeInBits(AS);
1391 assert(getLoadStoreAddressSpace(Instrs[I]) == AS);
1442 // `Offset` might not have the expected number of bits, if e.g. AS has a