drm2/radeon/radeon_state.c

877 				     drm_radeon_clear_t * clear,
886 	unsigned int flags = clear->flags;
905 			DRM_ERROR("radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
915 		 * 2D fill to clear the front or back buffer.
920 		OUT_RING(clear->color_mask);
951 				OUT_RING(clear->clear_color);
973 				OUT_RING(clear->clear_color);
983 	/* hyper z clear */
997 		u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
998 		    ((clear->depth_mask & 0xff) << 24);
1009 			   just to the max (0xff? or actually 0x3fff?), need to take z clear
1013 			   only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
1014 			   other ones are ignored, and the same clear mask can be used. That's
1015 			   very different behaviour than R200 which needs different clear mask
1016 			   and different number of tiles to clear if hierz is enabled or not !?!
1020 			/* clear mask : chooses the clearing pattern.
1021 			   rv250: could be used to clear only parts of macrotiles
1024 			   not clear tile (or maybe one of the bits indicates if the tile is
1025 			   compressed or not), bit 2 and 3 to not clear tile 1,...,.
1030 			   rv100: clearmask covers 2x8 4x1 tiles, but one clear still
1054 				   the tile cache like r100, but just needs to clear the hi-level z-buffer?
1073 					/* the number of tiles to clear */
1075 					/* clear mask : chooses the clearing pattern. */
1096 					   directly address/clear 4x4 tiles instead of 8x2 * 4x4
1097 					   macro tiles, though would still need clear mask for
1100 					/* the number of tiles to clear */
1102 					/* clear mask : chooses the clearing pattern. */
1123 					/* the number of tiles to clear */
1125 					/* clear mask : chooses the clearing pattern. */
1133 		/* TODO don't always clear all hi-level z tiles */
1139 			   just to the max (0xff? or actually 0x3fff?), need to take z clear
1151 	/* We have to clear the depth and/or stencil buffers by
1216 			tempRB3D_STENCILREFMASK = clear->depth_mask;
1292 			rb3d_stencilrefmask = clear->depth_mask;	/* misnamed field */
1360 	/* Increment the clear counter.  The client-side 3D driver must
1361 	 * wait on this value before performing the clear ioctl.  We
2161 	drm_radeon_clear_t *clear = data;
2172 	if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes,
2176 	radeon_cp_dispatch_clear(dev, file_priv->masterp, clear, depth_boxes);