binutils/opcodes/arm-dis.c

90    %y<code>		print a single precision VFP reg.
92    %z<code>		print a double precision VFP reg
1723 			  func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
1864 			      func (stream, "<illegal reg q%ld.5>", value >> 1);
2423 			int reg = raw_reg & ((4 << size) - 1);
2426 			func (stream, "d%d[%d]", reg, ix);
2564 			  func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2626 			      func (stream, "<illegal reg q%ld.5>", value >> 1);
2798 			int reg;
2801 			for (reg = 0; reg < 16; reg++)
2802 			  if ((given & (1 << reg)) != 0)
2807 			      func (stream, "%s", arm_regnames[reg]);
3090 		  long reg;
3092 		  reg = (given >> 3) & 0x7;
3094 		    reg += 8;
3096 		  func (stream, "%s", arm_regnames[reg]);
3102 		  long reg;
3104 		  reg = given & 0x7;
3106 		    reg += 8;
3108 		  func (stream, "%s", arm_regnames[reg]);
3123 		  int reg;
3129 		  for (reg = 0; (reg < 8); reg++)
3130 		    if ((given & (1 << reg)) != 0)
3135 			func (stream, "%s", arm_regnames[reg]);
3191 			long reg;
3198 			reg = given >> bitstart;
3199 			reg &= (2 << (bitend - bitstart)) - 1;
3203 			    func (stream, "%s", arm_regnames[reg]);
3207 			    func (stream, "%ld", reg);
3211 			    func (stream, "%ld", reg << 1);
3215 			    func (stream, "%ld", reg << 2);
3223 			      (((pc + 4) & ~3) + (reg << 2), info);
3227 			    func (stream, "0x%04lx", reg);
3231 			    reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3232 			    info->print_address_func (reg * 2 + pc + 4, info);
3236 			    func (stream, "%s", arm_conditional [reg]);
3405 		  unsigned int reg = (given & 0x0000000fu);
3411 		  func (stream, "%s", arm_regnames[reg]);
3568 		  int reg;
3571 		  for (reg = 0; reg < 16; reg++)
3572 		    if ((given & (1 << reg)) != 0)
3577 			func (stream, "%s", arm_regnames[reg]);
3803   if (CONST_STRNEQ (option, "reg-names-"))
4231     fprintf (stream, "  reg-names-%s %*c%s\n",