Copy stable/9 to releng/9.3 as part of the 9.3-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

MFC r227730:

Initial version of cesa(4) driver for Marvell crypto engine and security
accelerator.

The following algorithms and schemes are supported:
- 3DES, AES, DES
- MD5, SHA1

Obtained from: Semihalf
Written by: Piotr Ziecik

MFC r232512:

Remove unused #defines. All this is now retrieved from the device tree.

MFC r226173, r227843, r227848 and r227908:
Use DEVMETHOD_END to mark end of device methods.
Remove superfluous device methods.
Add some missing __FBSBID() macros.

Copy head to stable/9 as part of 9.0-RELEASE release cycle.

Approved by: re (implicit)

Do not call platform_gpio_init() early. It doesn't work because we do
not have enough information to reliably setup GPIO pins. Do it when
we attach the gpio driver. This prevents hangs and the need to fake
up a softc.

Set preload_addr_relocate accordingly so that preloaded modules and
images are properly relocated.

Typo

Submitted by: Damjan Marion <damjan dot marion at gmail dot com>
MFC after: 3 days

Add basic support for the Marvell Orion TS-7800.

Submitted by: Kristof Provost <kristof -at- freebsd.org>

Fix mv_gpio_in() for pin numbers that occupy bits 8-31 in GPIO registers.
The compiler will truncate the 32-bit return value of mv_gpio_value_get()
to match the 8-bit return value of mv_gpio_in(). A conditional expression
is used to have mv_gpio_in() always return 0 or 1 instead.

In arm_get_next_irq(), use the last IRQ argument in order to prevent
a hard hang due to an interrupt storm or stuck interrupt pin. We
return the next IRQ that is larger than the last one returned and
in doing so give all interrupts a fair chance of being handled.
Consequently, we're able to break into the kernel debugger in such
an event.

o Make sure to mask off timer1 interrupts. It's not necessarily
masked-off by the firmware.
o In DELAY(). Make sure we have an inner-loop body that the compiler
cannot eliminate. While timing does not have to be perfect, the
loops must be there to have at least some notion of delay.

Obtained from: Juniper Networks

Remove use_high from the softc and simply check the number of GPIO
pins to determine whether there's a high register set or not. This
allows platform_gpio_init() to work without duplicating the work
done in the attach method.

The FDT describes the host controller directly. There's no need to
get properties from the parent. The parent is in fact the FDT bus
itself and will therefore not have the properties we're looking
for.

Sponsored by: Juniper Networks

Fix r217688. We need to call init_param1() before we use msgbufsize,
now that the size of the message buffer is a tunable.

Fix backtraces by defining ksym_start & ksym_end if DDB is
defined. The kernel linker doesn't deal with symbols of
type NOTYPE and typically gives the wrong symbol ($a) for
local symbols.

Obtained from: Juniper Networks, Inc.

Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.

Submitted by: perryh pluto.rain.com (previous version)
Reviewed by: jhb
Approved by: kib (mentor)
Tested by: universe

- Add a proper return value to mv_gpio_intr().
- Remove an obsolete use of INTR_FAST.

Set of legacy mode SATA enchancements:
- Implement proper combined mode decoding for Intel controllers to properly
identify SATA and PATA channels and associate ATA channels with SATA ports.
This fixes wrong reporting and in some cases hard resets to wrong SATA ports.
- Improve SATA registers support to handle hot-plug events and potentially
interface errors. For ICH5/6300ESB chipsets these registers accessible via
PCI config space. For later ones they may be accessible via PCI BAR(5).
- For controllers not generating interrupts on hot-plug events, implement
periodic status polling. Use it to detect hot-plug on Intel and VIA
controllers. Same probably could also be used for Serverworks and SIS.

Clear timer interrupt status before calling callback, not after it,
This fixes timer interrupt losses, fatal in one-shot mode.

Fix several un-/signedness bugs of r210290 and r210293. Add one more check.

Refactor Marvell ARM SoC timer driver to the new timer infrastructure.

Now that we are fully FDT-driven on MRVL platforms, remove PHYSMEM_SIZE option.

Eliminate FDT_IMMR_VA define.

This removes platform dependencies from <machine>/fdt.h for the benfit of
portability.

Move MRVL FDT fixups and PIC decode routine to a platform specific area.

This allows for better encapsulation (and eliminates generic fdt_arm.c, at
least for now).

Convert Marvell ARM platforms to FDT convention.

The following systems are involved:

- DB-88F5182
- DB-88F5281
- DB-88F6281
- DB-78100
- SheevaPlug

This overhaul covers the following major changes:

- All integrated peripherals drivers for Marvell ARM SoC, which are
currently in the FreeBSD source tree are reworked and adjusted so they
derive config data out of the device tree blob (instead of hard coded /
tabelarized values).

- Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
good by to obio / mbus drivers and numerous hard-coded config data.

Note that world needs to be built WITH_FDT for the affected platforms.

Reviewed by: imp
Sponsored by: The FreeBSD Foundation.

Import mvs(4) - Marvell 88SX50XX/88SX60XX/88SX70XX/SoC SATA controllers
driver for CAM ATA subsystem. This driver supports same hardware as
atamarvell, ataadaptec and atamvsata drivers from ata(4), but provides
many additional features, such as NCQ, PMP, etc.

Oops! Wrong copy-paste in r206053.

Fill extended ATA command registers in cPRD to support 48bit commands.

Provide correct TCLK value for Kirkwood A1 silicon revision.

While there improve SOC ID output accordingly.

Obtained from: Semihalf
MFC after: 1 week

Do not force verbose and single mode in non-metadata boot case.

We want to go multi-user by default also in case of booting without loader(8).

Fix the build.

MFp4:
Introduce ATA_CAM kernel option, turning ata(4) controller drivers into
cam(4) interface modules. When enabled, this options deprecates all ata(4)
peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers
(ada, cd, ...) and interfaces to be natively used instead.

As side effect of this, ata(4) mode setting code was completely rewritten
to make controller API more strict and permit above change. While doing
this, SATA revision was separated from PATA mode. It allows DMA-incapable
SATA devices to operate and makes hw.ata.atapi_dma tunable work again.

Also allow ata(4) controller drivers (except some specific or broken ones)
to handle larger data transfers. Previous constraint of 64K was artificial
and is not really required by PCI ATA BM specification or hardware.

Submitted by: nwitehorn (powerpc part)

Eliminate an unnecessary vm include file.

MFp4:
- Remove most of direct relations between ATA(4) peripherial and controller
levels. It makes logic more transparent and is a mandatory step to wrap
ATA(4) controller level into ATA-native CAM SIM.
- Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger
I/O transaction sizes without additional cost.

Review previous change. It has no relation to the I-cache coherency
changes and thus unintentional.

Spotted by: rdivacky@

o Introduce vm_sync_icache() for making the I-cache coherent with
the memory or D-cache, depending on the semantics of the platform.
vm_sync_icache() is basically a wrapper around pmap_sync_icache(),
that translates the vm_map_t argumument to pmap_t.
o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc
it replaces the pmap_page_executable() function, added to solve
the I-cache problem in uiomove_fromphys().
o In proc_rwmem() call vm_sync_icache() when writing to a page that
has execute permissions. This assures that when breakpoints are
written, the I-cache will be coherent and the process will actually
hit the breakpoint.
o This also fixes the Book-E PMAP implementation that was missing
necessary locking while trying to deal with the I-cache coherency
in pmap_enter() (read: mmu_booke_enter_locked).

The key property of this change is that the I-cache is made coherent
*after* writes have been done. Doing it in the PMAP layer when adding
or changing a mapping means that the I-cache is made coherent *before*
any writes happen. The difference is key when the I-cache prefetches.

Introduce SheevaPlug support.

- The device is based on Marvell 88F6281 system on chip.
- More info about the platform at http://www.plugcomputer.org

- To build the FreeBSD kernel:
make buildkernel TARGET_ARCH=arm KERNCONF=SHEEVAPLUG

- Installation notes at: http://wiki.freebsd.org/FreeBSDMarvell

Submitted by: Michal Hajduk
Obtained from: Semihalf

Exclude common Kirkwood settings so they can be shared among various platforms
based on this SOC. This is a preliminary step for SheevaPlug support.

Submitted by: Michal Hajduk
Obtained from: Semihalf

Properly handle initial state of power mgmt.

Modules on Marvell SOC can be selectively PM-disabled, and we must not access
disabled devices' registers (attempt to initialize them) unconditionally, as
this leads to the system hang. This patch introduces graceful handling of the
PM state during devices init.

Submitted by: Michal Hajduk
Obtained from: Semihalf

Eliminate platform_pmap_init() to simplify Marvell bootstrap code.

Map DPCPU pages into ARM kernel VA space.

DPCPU area was not properly mapped into kernel VA space, which caused page
fault on the first DPCPU access. This patch fixes the problem by mapping DPCPU
area into kernel VA space.

Submitted by: Michal Hajduk, Piotr Ziecik
Reviewed by: cognet, stas
Approved by: re (kib)
Obtained from: Semihalf

Enable all populated TWSI (I2C) controllers on Marvell SOCs.

Obtained from: Semihalf

Introduce ata(4) support for Marvell integrated SATA controllers (found on
88F5xxx, 88F6xxx and MV78xxx system on chip devices).

Reviewed by: stas
Obtained from: Semihalf

Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
PCPU_*. Requires only one extra instruction more than PCPU_* and is
virtually the same as __thread for builtin and much faster for shared
objects. DPCPU variables can be initialized when defined.
- Modules are supported by relocating the module's per-cpu linker set
over space reserved in the kernel. Modules may fail to load if there
is insufficient space available.
- Track space available for modules with a one-off extent allocator.
Free may block for memory to allocate space for an extent.

Reviewed by: jhb, rwatson, kan, sam, grehan, marius, marcel, stas

Move the memory layout definitions and logic from mvreg.h to mvwin.h
so that it isn't exposured unless needed. In particular this means
that it's easier to tune the memory layout based on board details.
While here, remove inclusion of <machine/intr.h> from mvreg.h. This
also contains exposure to SoC specifics in MI drivers, because NIRQ
depends on the SoC.

strict kobj signatures: number of fixes for arm architecture

no functional changes should result

Reviewed by: imp, current@
Approved by: jhb (mentor)

Pass the previously returned IRQ back to arm_get_next_irq() so that
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.

Obtained from: Juniper Networks, Inc.

Adjust Marvell Discovery (MV78xxx) support to recognize newest chip revisions,
handle Z0 revision (early silicon) explicitly due to its quirks.

Obtained from: Marvell, Semihalf

Fix path and config name for ehci_mbus.c

Include Marvell EHCI HC driver for USB2.

Check PCIE link status before accessing the bus.

Some 88F5182-based systems (Linkstation) have problems when PCIE is
accessed without any peripherals present.

Rename Marvell ARM CPU specific file according to r186933.

Improve Marvell SOCs PCI/PCIE driver.

- Provide dedicated rmans for MEM and IO resources.

- Convert PCI IRQ routing info into a table (from callback approach), provide
config data for alternative DB- boards.

- Fix a wrong boundary check error in pcib_mbus_init_bar()

Obtained from: Semihalf

Improve and extend Marvell SOCs platform code.

- Allow for setting per platform MPP/GPIO configuration in the kernel, so
that we can override all settings firmware might set.

- Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR.

- Improve handling of USB controllers so that all port are available on the
given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of
USB decode windows set-up.

- Other minor fixes and cosmetics.

Obtained from: Semihalf

Minor style(9) corrections.

Adjust Marvell SOC support for A0 chip revision.

- Clean up TCLK handling so that it's dynamically recognized depending on
registers settings or chip version/revision. Update registers definitions.

- Teach SOC ident routine about A0 (initial silicon version for general
audience)

Obtained from: Marvell, Semihalf

Avoid confusion and adjust link address range of Marvell Orion kernel so it is
the same as for Kirkwood and Discovery.

Fix configuration of the PCI bridge. This got omitted in the initial import of
this code.

- Fix spelling error in comments.

PR: arm/128891
Submitted by: Pavel Pankov <pankov_p@mail.ru>
Approved by: kib (mentor)

Improve error handling in pcib_mbus_identify().

Improve style(9) and other cosmetics in Marvell SOCs code.

Fix off-by-one error in mbus_attach().

PCI/PCI-Express support for Marvell systems.

Obtained from: Marvell, Semihalf

Auto-size kernel page tables allocation on Marvell systems.

This allows mini dumps to fully work for these platforms.

Obtained from: Juniper Networks, Semihalf

Introduce basic support for Marvell families of system-on-chip ARM devices:

* Orion
- 88F5181
- 88F5182
- 88F5281

* Kirkwood
- 88F6281

* Discovery
- MV78100

The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:

* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART

Other peripherals drivers will be introduced separately.

Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf