Copy stable/10@r272459 to releng/10.1 as part of
the 10.1-RELEASE process.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

MFC 265852: Map device memory using PTE_DEVICE rather than PTE_NOCACHE.

MFC 265694, 265705, 265784:

Move the mptramp code which is specific to the Marvell ArmadaXP SoC out of
the common locore.S file and into the mv/armadaxp directory.

Consolidate all the AP core startup stuff under a single #ifdef SMP block

Call idcache_inv_all from the AP core entry code before turning on the MMU.
Also, enable instruction and branch caches, which should be safe now that
they're properly initialized/invalidated first.

MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,
263030, 263033, 263034, 263056, 263057,

Remove all the redundant external declarations of exception vectors and
runtime setting of the pointers that's scattered around various places.

Remove all traces of support for ARM chips prior to the arm9 series.

Make the default exception handler vectors point to where I thought they
were already pointing: the default handlers (not a panic that says there
is no default handler).

Eliminate irq_dispatch.S. Move the data items it contained into
arm/intr.c and the functionality it provided into arm/exception.S.

Move the exception vector table (so-called "page0" data) into exception.S
and eliminate vectors.S.

Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.

Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros.

Now that the PUSHFRAME and PULLFRAME macros are used only in the swi
entry/exit code, they don't need to be macros. Except that didn't work
and the whole change was reverted.

Remove some unnecessary indirection and jump right to the handler functions.

Use panic rather than printf to "handle" an arm26 address exception
(should never happen on arm32).

Remove the unreferenced DATA() macro.

Remove #include <machine/asmacros.h> from files that don't need it.

MFC 257774, 256760, 262916, 262905, 262918, 262919, 262920, 262921, 262924,
262925, 262929, 262932, 262935, 262940, 262941, 262942, 262948, 262949,
262950

Strip arm/conf/DEFAULTS down to just items that are mandatory for running
the architecture.

Move all the files named foo/common.c to foo/foo_common.c

Initial cut for DTS on the hl201 board.

Add commented out dts for sam9260ek as well as early printf support.

Make clock optional on uart nodes, then back it out ("I don't know what I
was thinking, but it is lame.")

Set the baud rate if it isn't 0

Make at91_soc_id() public.

Properly round at91 resource on unmapping.

Move AT91 AIC related stuff to own file.

Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in
LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32.

Follow r262916 with one more config file that references a renamed common.c

Remove bogus AT91 define that causes compile errors. Most of the defines
for SAM9X are going away soonish anyway (once FDT works), but until
then...

Remove all dregs of a per-thread undefined-exception-mode stack.

Rework the VFP code that handles demand-based save and restore of state.

Always call vfp_discard() on thread death.

When a thread begins life it doesn't own the VFP hardware state on any cpu.

Make undefined exception entry MP-safe.

MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,
r262585, r262587, r262696, r262712

Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c.

aicasm: Don't complain about missing prototypes to ease bootstrap issues.

Vybrid: Add driver for Inter-Integrated Circuit (I2C).

imx6: Initialize the Low Power Mode bits to keep the ARM cores running
during WFI.

All our current ARM multi-core systems have all cores in one package with
a shared L2 cache, reflect that in the common cpu_topo() routine.

mpcore timer: Supply a DELAY() implementation via weak linkage, so that
SoC-specific code can supply a better implementation.

imx6: Add some rudimentary voltage control.

Add an armv7 implementation of cpu_sleep().

Add __used attribute so that the DELAY implementation doesn't get
optimized away as unreferenced, causing linker errors when trying to
resolve the weak reference to the missing function.

MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,
r262482, r262483, r262531,

Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files.

If the L2 cache type is PIPT, pass a physical address for a flush.

Actually set the proper bit to indicate TTB shared memory.

Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support.

Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.

Add the bits needed to run SMP on imx6.

Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.

Minor tweaks to the imx GPT timer

Vybrid enhancements...
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
- Add support for Quartz Module.
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock

MFC r261423, r261424, r261516, r261513, r261562, r261563, r261564, r261565,
r261596, r261606

Add the imx sdhci controller.

Move Open Firmware device root on PowerPC, ARM, and MIPS systems to
a sub-node of nexus (ofwbus) rather than direct attach under nexus. This
fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier.
SPARC is unchanged.

Add the missing ')' at end of sentence. Reword it to use a more common idiom.

Pass the kernel physical address to initarm through the boot param struct.

Make functions only used in vfp.c static, and remove vfp_enable.

Fix __syscall on armeb EABI. As it returns a 64-bit value it needs to
place 32-bit data in r1, not r0. 64-bit data is already packed correctly.

Use abp_physaddr for the physical address over KERNPHYSADDR. This helps us
remove the need to load the kernel at a fixed address.

Remove references to PHYSADDR where it's used only in debugging output.

Dynamically generate the page table. This will allow us to detect the
physical address we are loaded at to change the mapping.

MFC r261410

Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

MFC r261351, r261352, r261355, r261396, r261397, r261398, r261403, r261404,
r261405

Open Firmware interrupt specifiers can consist of arbitrary-length byte
strings and include arbitrary information (IRQ line/domain/sense). When the
ofw_bus_map_intr() API was introduced, it assumed that, as on most systems,
these were either 1 cell, containing an interrupt line, or 2, containing
a line number plus a sense code. It turns out a non-negligible number of
ARM systems use 3 (or even 4!) cells for interrupts, so make this more
general.

Provide a simpler and more standards-compliant simplebus implementation to
get the Routerboard 800 up and running with the vendor device tree. This
does not implement some BERI-specific features (which hopefully won't be
necessary soon), so move the old code to mips/beri, with a higher attach
priority when built, until MIPS interrupt domain support is rearranged.

Allow nesting of simplebuses.

Add a set of helpers (ofw_bus_get_status() and ofw_bus_status_okay()) to
process "status" properties of OF nodes.

Fix one remnant endian flaw in nexus.

MFC r261252, r261279, r261304, r261305, r261322, r261336, r261337, r261338,
r261353

Fix the name of the dts file for the HL201...

When mapping an address, the bsh needs the same offset we do for other things.

Add explicit depends on bus_if.h and device_if.h to avoid a
chicken and egg problem in some compilation environments.

Switch to using PAs rather than VAs for the addresses we map for
devices. This is a nop, except for what's reported by atmelbus for the
resources.

Comment cleanups. Move things around for diff reduction against FDT work.

MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,
r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373,
r260374, r260375

Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs.
Correct license statements to reflect the fact that these files were all
derived from sys/arm/mv/bus_space.c.

In pmap_unmapdev(), remember the size, and use that as an argument to
kva_free(), or we'd end up always passing it a size of 0

In pmap_mapdev(), first check whether a static mapping exists,

Convert TI static device mapping to use the new arm_devmap_add_entry(),

Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy.

Eliminate use of fdt_immr_addr(), it's not needed for tegra

Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make
static device mappings.

Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.

Add #include <machine/fdt.h> to a few files that used to get it via pollution

Enable the mv cesa security/crypto device by providing the required property
in the dts source, and adding the right devices to the kernel config.

Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs,
related to setting up static device mappings. Since it was only used by
arm/mv/mv_pci.c, it's now just static functions within that file, plus
one public function that gets called only from arm/mv/mv_machdep.c.

Switch RPi to using arm_devmap_add_entry() to set up static device mapping.

Allow 'no static device mappings' to potentially work.

Don't try to find a static mapping before calling pmap_mapdev(), that logic
is now part of pmap_mapdev() and doesn't need to be duplicated here.

Switch a10 to using arm_devmap_add_entry() to set up static device mapping.

MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,
r257282, r257332

Wait for DesignWare UART transfers completion before accessing line control

Enable UART busy detection handling for Armada XP - based board

Enable SATA interface on Armada XP
Run mvs SATA driver on Armada XP instead of old mv_sata

Retire arm_remap_nocache() and the data and constants associated with it.

Remove hard-coded mappings related to Armada XP support

Fix-up DTB for Armada XP registers' base according to the actual settings

Change Armada XP kernel load address to the u-boot's end address

Remove not working and deprecated PJ4Bv6 support

Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

Add missing ARMv6 CPU functions to ARM Makefile

MFC r258800, r258802, r258805, r258806, r258807, r258851, r258857,
r259199, r259484, r259513, r259514, r259516

The kernel stack guard pages are only below the stack pointer, not above.

Remove unnecessary double-setting of the thread's onfault state in
copyinstr().

Open Firmware mandates that certain cross-references, in particular those
in /chosen, be ihandles. The ePAPR spec makes those cross-reference phandles,
since FDT has no concept of ihandles. Have the OF FDT CI module interpret
queries about ihandles as cross-reference phandles.

Real OF systems have an ihandle under /chosen/stdout, not a phandle. Use
the right type.

Rearchitect platform memory map parsing to make it less
Open Firmware-centric.

Remove fdtbus_bs_tag definition, which is now obsolete. The remainder of
this file is also slated for future demolition.

Return the correct IEEE 1275 code for "nextprop".

Use the common Open Firmware PCI interrupt routing code instead of the
duplicate version in dev/fdt.

Configure interrupt sense based on device tree information.

Simplify the ofw_bus_lookup_imap() API slightly: make it allocate maskbuf
internally instead of requiring the caller to allocate it.

MFC r257702, r257745, r257746, r257747, r257751, r257791, r257793,
r257794, r257795, r257992

Teach nexus(4) about Open Firmware (e.g. FDT) on ARM and MIPS, retiring
fdtbus in most cases.

Make OF_nextprop() work correctly for FDT by using the libfdt
fdt_next_property_offset() API.

Do not panic if pmap_mincore() is called.

An addendum: it is possible, though of questionable utility, for a node
to have no properties at all.
Add definition for the Atheros 8021 gigabit PHY.

Consolidate Apple firmware hacks and improve them by switching on the
presence of mac-io devices in the tree, which uniquely identifies Apple
hardware.

Allow OF_decode_addr() to also be able to map resources on big-endian
devices.

Make tsec work with the device tree present on the RB800.

Be more flexible about which compatible strings to accept. This brings up
the PCI Express bus on the RB800 using the firmware device tree.

Rename the "bare" platform "mpc85xx", which is what it actually is, and
add actual platform probing based on PVR.

MFC r256932, r256938, r256966, r256953, r256967, r256969, r257015:

Add a new function (OF_getencprop()) that undoes the transformation applied
by encode-int. Specifically, it takes a set of 32-bit cell values and
changes them to host byte order. Most non-string instances of OF_getprop()
should be using this function, which is a no-op on big-endian platforms.

Use the new function all over the place.

MFC r258779,r258780,r258787,r258822:

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.

Similar to the (1 << 31) case it is not defined to do (2 << 30).

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

MFC r257669, r257672, r257673, r257676, r257678:

Call initarm_lastaddr() later in the init sequence, after establishing
static device mappings, rather than as the first of the initializations
that a platform can hook into. This allows a platform to allocate KVA
from the top of the address space downwards for things like static device
mapping, and return the final "last usable address" result after that and
other early init work is done.

Because some platforms were doing work in initarm_lastaddr() that needs to
be done early, add a new initarm_early_init() routine and move the early
init code to that routine on those platforms.

Make PTE_DEVICE a synonym for PTE_NOCACHE on armv4, to make it easier to
share the same code on both architectures.

Add new helper routines for arm static device mapping. The new code
allocates kva space from the top down for the device mappings and builds
entries in an internal table which is automatically used later by
arm_devmap_bootstrap(). The platform code just calls the new
arm_devmap_add_entry() function as many times as it needs to (up to 32
entries allowed; most platforms use 2 or 3 at most).

Remove imx local devmap code and use the essentially identical common
code that got moved from imx_machdep.c to arm/devmap.c.

MFC r257648, r257649, r257660:

Begin reducing code duplication in arm pmap.c and pmap-v6.c by factoring
out common code related to mapping device memory into a new devmap.c file.

Remove the growing duplication of code that used pmap_devmap_find_pa() and
then did some math with the returned results to generate a virtual address,
and likewise in reverse to get a physical address. Now there are a pair
of functions, arm_devmap_vtop() and arm_devmap_ptov(), to do that. The
bus_space_map() implementations are rewritten in terms of these.

Move remaining code and data related to static device mapping into the
new devmap.[ch] files. Emphasize the MD nature of these things by using
the prefix arm_devmap_ on the function and type names (already a few of
these things found their way into MI code, hopefully it will be harder to
do by accident in the future).

MFC r257201, r257202

Retire arm_remap_nocache() and the data and constants associated with it.

MFC r257199, r257200, r257217:

Remove all #include <machine/pmap.h> from arm code. It's already
included by vm/pmap.h, which is a prerequisite for arm/machine/pmap.h
so there's no reason to ever include it directly.

Remove #include <machine/frame.h> from all the arm code that doesn't
really need it. That would be almost everywhere it was included. Add
it in a couple files that really do need it and were previously getting
it by accident via another header.

Remove the last dregs of trapframe_t. It turns out only arm was using
this type, so remove it to make arm code more consistant with other
platforms.

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Replace kernel virtual address space allocation with vmem. This provides
transparent layering and better fragmentation.

- Normalize functions that allocate memory to use kmem_*
- Those that allocate address space are named kva_*
- Those that operate on maps are named kmap_*
- Implement recursive allocation handling for kmem_arena in vmem.

Reviewed by: alc
Tested by: pho
Sponsored by: EMC / Isilon Storage Division

Fix the passing of time on Armada XP.

In order to become independent of Coherency Fabric frequency, configure
Timer and Watchdog to operate in 25MHz mode.

Submitted by: Zbigniew Bodek <zbb@semihalf.com>

decode_win_sdram_fixup() function should be declared, defined and used
only by Armada XP

Obtained from: Semihalf

Disable decoding windows with no FDT entry.

- On ARMADAXP B0 (GP development board) we are not able to use PCI due to
whole 32-bit address space used by 4GB of RAM memory.
- Change is required to destroy unnecessary window to free address space
for PCI and other devices
- Fix offset value for SDRAM decoding windows

Obtained from: Semihalf

Properly initialize Armada XP MP subsystem.

- correct setting of Auxiliary Control Register for MP mode
- correct setting of Auxiliarty Debug registers
- cleanup management of memory contains bootup code
- early initialization of Coherency Fabric (MP and not-MP mode)
- enable Snoop Filtering

Obtained from: Semihalf

Initialize L2 cache for Armada XP.

Obtained from: Semihalf

Move initialization of CESA decoding windows from common section
to driver specific files.

- window initialization is done during device attach
- CESA TDMA decoding windows values are set based on DTS,
not copied from CPU registers
- remove unnecessary virtual mapping
- update dts file

Obtained from: Semihalf

MFcalloutng:
Switch eventtimers(9) from using struct bintime to sbintime_t.
Even before this not a single driver really supported full dynamic range of
struct bintime even in theory, not speaking about practical inexpediency.
This change legitimates the status quo and cleans up the code.

Add a default do-nothing implementation of fdt_pci_devmap() using a weak alias,
so that we don't need an empty implementation of it for every Marvell platform
that has no PCI. This allows the removal of the SheevaPlug-specific stub and
config files, and eliminates the need to add similar stubs for future models.

Marvell platforms that do expose PCI are compiled with 'device pci' which
causes the real (non-weak) implementation in dev/fdt/fdt_pci.c to be used.

Approved by: cognet (mentor)

Allow building LINT by defining both SAMPLE_AT_RESET on the one hand
and SAMPLE_AT_RESET_{LO|HI} on the other. It doesn't matter which
values they take, as long as they are defined.

Merge the FDT versions of initarm.

The copies of initarm used on platforms with FDT support were almost
identical. The differences were pulled out into separate functions that
were called by initarm.

This change merges the, now identical, copies of initarm and a few of it's
support functions. This is a step towards a common kernel on ARMv6.

Fix build for SMP.

Submitted by: Giovanni Trematerra <gianni at freebsd DOT org>

Merge r242125 into the other ARMv6 copies of initarm.

Pull out the SoC specific parts of initarm into separate functions

Reduce the diff between the FDT implementations of initarm.
This only touches whitespace and comments.

Create a common set_stackptrs in sys/arm/machdep.c.

On single core devices set_stackptrs is only ever called with cpu = 0 in
initarm and will be identical to the existing function. On SMP this needs
to be implemented for sys/arm/mp_machdep.c, but the implementations are
identical for each SoC.

Implement MSI support.

MSI are implemented via Inbound Shared Doorbell 1 interrupts. Interrupts
are triggered by writing to Software Triggered Interrupt registeri (PCIe
card using physical address of this register in BAR0 space). There are 32
interrupts available. It can be increased by using Doorbell 2 and
Doorbell 3 registers to 96 interrupts.

Obtained from: Marvell, Semihalf

Add support for MSI in interrupt controlller.

MSI are implemented via software interrupt. PCIe cards will write
into software interrupt register which will cause inbound shared
interrupt which will be interpreted as a MSI.

Obtained from: Marvell, Semihalf

Remove unused structure fields

Obtained from: Semihalf

Enable PCI for Armada XP

Obtained from: Semihalf

pci: Implement new memory and io space allocator for PCI.

Cleanup code and move initializing bridge into separate function.
Add checking of PCI mode (RC or endpoint).

Obtained from: Semihalf

Add support for Armada XP A0.

- Add functions to calculate clocks instead using hardcoded values
- Update reset and timers functions
- Update number of interrupts
- Change name of platform from db88f78100 to db78460
- Correct DRAM size and PCI IRQ routing in dts file.

Obtained from: Semihalf

- Calculate the I2C baud rate to keep them <100 kHz under different TCLK
frequencies. The maximum freqency is 100 kHz according to the datasheet.

- Add child device probing support based on the device tree. It now tries to
find i2c-address property in the tree and attach the device with given slave
address to iicbus.

Add mvts(4) driver for internal thermal sensor found on 88F6282 and 88F6283.
The temperature value will be exported via sysctl like this:

dev.mvts.0.temperature: 52.1C

Sort IDs.

- MV_DEV_88F6282 has 256KB 4-way L2 cache.
- Sort IDs in win_cpu_can_remap() and remove MV_DEV_MV78100 because it is
included in MV_DEV_DISCOVERY.
- Add MV_DEV_MV78XXX to xor_max_eng().

Fix a bug that could fail to initialize GPIO pins specified in "gpios" because
"gpio-controller" property at the controller node was always ignored.

Set machine correctly on ARM. This allows universe to use the correct world
when building each kernel.

Reviewed by: imp

Merging of projects/armv6, part 7

Add Marvell ARMADA XP support

Obtained from: Marvell, Semihalf

Add support for Marvell 88F6282.

Sponsored by: Plat'Home, Co.,Ltd.

Remove some unused variables/externs that have been copied too many times...

Fix LINT.

Obtained from: Juniper Networks, Inc.

More Linux boot support. Create arm_dump_avail_init() to initialize
this array either from Linux boot data, when enabled, or in the
typical way that most ports do it. arm_pyhs_avail_init is coming
soon since it must be a separate function.

Create default_parse_boot_param which, if FreeBSD /boot/loader support
is enabled, sets values based on the metadata passed in. Otherwise
fake_preload_metadata is called. Change the default parse_boot_param
to default_parse_boot_param. Enable this functionality only on the mv
platform, which is where most of the code is from.

Reviewed by: cognet, Ian Lapore

Modify all the arm platform files to call parse_boot_param passing in
the boot parameters from initarm first thing. parse_boot_param parses
the boot arguments and converts them to the /boot/loader metadata the
rest of the kernel uses. parse_boot_param is a weak alias to
fake_preload_metadata, which all the platforms use now, but may become
more extensive in the future.

Since it is a weak symbol, specific boards may define their own
parse_boot_param to interface to custom boot loaders.

Reviewed by: cognet@, Ian Lapore

Trim trailing whitespace...

Pull out the common code to initialise proc0 & thread0 from initarm to a
common function.

Reviewed by: imp

Minor rearrangement of the locore <-> initarm interface. Pass in a
structure with the first 4 registers to allow a wider range of boot
loaders to work. Future commits will make use of this to centralize
support for the different loaders.

Unbreak LINT for ARM: DEBUG is a kernel configuration option.

Add localbus driver for Marvell's platforms.

Obtained from: Semihalf
Supported by: FreeBSD Foundation, Juniper Networks

Add architecture dependent code to support NAND Framework on Marvell SoCs.

Obtained from: Semihalf
Supported by: FreeBSD Foundation, Juniper Networks

Fix error check.

Submitted by: Lukasz Plachno
Obtained from: Semihalf

Remove unused #defines. All this is now retrieved from the device tree.

MFC after: 1 week

Make sure we do not provide the page 0 to the VM. It can't handle it properly,
because pmap_extract() returns 0 when there's no mapping.

PR: arm/154227
MFC after: 1 week

Fix OF_finddevice error return value in case of FDT.

According to the open firmware standard, finddevice call has to return
a phandle with value of -1 in case of error.

This commit is to:
- Fix the FDT implementation of this interface (ofw_fdt_finddevice) to
return (phandle_t)-1 in case of error, instead of 0 as it does now.
- Fix up the callers of OF_finddevice() to compare the return value with
-1 instead of 0 to check for errors.
- Since phandle_t is unsigned, the return value of OF_finddevice should
be checked with '== -1' rather than '<= 0' or '> 0', fix up these cases
as well.

Reported by: nwhitehorn

Reviewed by: raj
Approved by: raj, nwhitehorn

- There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
(bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
since r52045) but even recently added device drivers do this unnecessarily.
Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
Discussed with: jhb
- Also while at it, use __FBSDID.

Initial version of cesa(4) driver for Marvell crypto engine and security
accelerator.

The following algorithms and schemes are supported:
- 3DES, AES, DES
- MD5, SHA1

Obtained from: Semihalf
Written by: Piotr Ziecik

Fix build when DEBUG is defined in the kernel configuration file (e.g.
LINT).

Do not call platform_gpio_init() early. It doesn't work because we do
not have enough information to reliably setup GPIO pins. Do it when
we attach the gpio driver. This prevents hangs and the need to fake
up a softc.

Set preload_addr_relocate accordingly so that preloaded modules and
images are properly relocated.

Typo

Submitted by: Damjan Marion <damjan dot marion at gmail dot com>
MFC after: 3 days

Add basic support for the Marvell Orion TS-7800.

Submitted by: Kristof Provost <kristof -at- freebsd.org>

Fix mv_gpio_in() for pin numbers that occupy bits 8-31 in GPIO registers.
The compiler will truncate the 32-bit return value of mv_gpio_value_get()
to match the 8-bit return value of mv_gpio_in(). A conditional expression
is used to have mv_gpio_in() always return 0 or 1 instead.

In arm_get_next_irq(), use the last IRQ argument in order to prevent
a hard hang due to an interrupt storm or stuck interrupt pin. We
return the next IRQ that is larger than the last one returned and
in doing so give all interrupts a fair chance of being handled.
Consequently, we're able to break into the kernel debugger in such
an event.

o Make sure to mask off timer1 interrupts. It's not necessarily
masked-off by the firmware.
o In DELAY(). Make sure we have an inner-loop body that the compiler
cannot eliminate. While timing does not have to be perfect, the
loops must be there to have at least some notion of delay.

Obtained from: Juniper Networks

Remove use_high from the softc and simply check the number of GPIO
pins to determine whether there's a high register set or not. This
allows platform_gpio_init() to work without duplicating the work
done in the attach method.

The FDT describes the host controller directly. There's no need to
get properties from the parent. The parent is in fact the FDT bus
itself and will therefore not have the properties we're looking
for.

Sponsored by: Juniper Networks

Fix r217688. We need to call init_param1() before we use msgbufsize,
now that the size of the message buffer is a tunable.

Fix backtraces by defining ksym_start & ksym_end if DDB is
defined. The kernel linker doesn't deal with symbols of
type NOTYPE and typically gives the wrong symbol ($a) for
local symbols.

Obtained from: Juniper Networks, Inc.

Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.

Submitted by: perryh pluto.rain.com (previous version)
Reviewed by: jhb
Approved by: kib (mentor)
Tested by: universe

- Add a proper return value to mv_gpio_intr().
- Remove an obsolete use of INTR_FAST.

Set of legacy mode SATA enchancements:
- Implement proper combined mode decoding for Intel controllers to properly
identify SATA and PATA channels and associate ATA channels with SATA ports.
This fixes wrong reporting and in some cases hard resets to wrong SATA ports.
- Improve SATA registers support to handle hot-plug events and potentially
interface errors. For ICH5/6300ESB chipsets these registers accessible via
PCI config space. For later ones they may be accessible via PCI BAR(5).
- For controllers not generating interrupts on hot-plug events, implement
periodic status polling. Use it to detect hot-plug on Intel and VIA
controllers. Same probably could also be used for Serverworks and SIS.

Clear timer interrupt status before calling callback, not after it,
This fixes timer interrupt losses, fatal in one-shot mode.

Fix several un-/signedness bugs of r210290 and r210293. Add one more check.

Refactor Marvell ARM SoC timer driver to the new timer infrastructure.

Now that we are fully FDT-driven on MRVL platforms, remove PHYSMEM_SIZE option.

Eliminate FDT_IMMR_VA define.

This removes platform dependencies from <machine>/fdt.h for the benfit of
portability.

Move MRVL FDT fixups and PIC decode routine to a platform specific area.

This allows for better encapsulation (and eliminates generic fdt_arm.c, at
least for now).

Convert Marvell ARM platforms to FDT convention.

The following systems are involved:

- DB-88F5182
- DB-88F5281
- DB-88F6281
- DB-78100
- SheevaPlug

This overhaul covers the following major changes:

- All integrated peripherals drivers for Marvell ARM SoC, which are
currently in the FreeBSD source tree are reworked and adjusted so they
derive config data out of the device tree blob (instead of hard coded /
tabelarized values).

- Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
good by to obio / mbus drivers and numerous hard-coded config data.

Note that world needs to be built WITH_FDT for the affected platforms.

Reviewed by: imp
Sponsored by: The FreeBSD Foundation.

Import mvs(4) - Marvell 88SX50XX/88SX60XX/88SX70XX/SoC SATA controllers
driver for CAM ATA subsystem. This driver supports same hardware as
atamarvell, ataadaptec and atamvsata drivers from ata(4), but provides
many additional features, such as NCQ, PMP, etc.

Oops! Wrong copy-paste in r206053.

Fill extended ATA command registers in cPRD to support 48bit commands.

Provide correct TCLK value for Kirkwood A1 silicon revision.

While there improve SOC ID output accordingly.

Obtained from: Semihalf
MFC after: 1 week

Do not force verbose and single mode in non-metadata boot case.

We want to go multi-user by default also in case of booting without loader(8).

Fix the build.

MFp4:
Introduce ATA_CAM kernel option, turning ata(4) controller drivers into
cam(4) interface modules. When enabled, this options deprecates all ata(4)
peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers
(ada, cd, ...) and interfaces to be natively used instead.

As side effect of this, ata(4) mode setting code was completely rewritten
to make controller API more strict and permit above change. While doing
this, SATA revision was separated from PATA mode. It allows DMA-incapable
SATA devices to operate and makes hw.ata.atapi_dma tunable work again.

Also allow ata(4) controller drivers (except some specific or broken ones)
to handle larger data transfers. Previous constraint of 64K was artificial
and is not really required by PCI ATA BM specification or hardware.

Submitted by: nwitehorn (powerpc part)

Eliminate an unnecessary vm include file.

MFp4:
- Remove most of direct relations between ATA(4) peripherial and controller
levels. It makes logic more transparent and is a mandatory step to wrap
ATA(4) controller level into ATA-native CAM SIM.
- Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger
I/O transaction sizes without additional cost.

Review previous change. It has no relation to the I-cache coherency
changes and thus unintentional.

Spotted by: rdivacky@

o Introduce vm_sync_icache() for making the I-cache coherent with
the memory or D-cache, depending on the semantics of the platform.
vm_sync_icache() is basically a wrapper around pmap_sync_icache(),
that translates the vm_map_t argumument to pmap_t.
o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc
it replaces the pmap_page_executable() function, added to solve
the I-cache problem in uiomove_fromphys().
o In proc_rwmem() call vm_sync_icache() when writing to a page that
has execute permissions. This assures that when breakpoints are
written, the I-cache will be coherent and the process will actually
hit the breakpoint.
o This also fixes the Book-E PMAP implementation that was missing
necessary locking while trying to deal with the I-cache coherency
in pmap_enter() (read: mmu_booke_enter_locked).

The key property of this change is that the I-cache is made coherent
*after* writes have been done. Doing it in the PMAP layer when adding
or changing a mapping means that the I-cache is made coherent *before*
any writes happen. The difference is key when the I-cache prefetches.

Introduce SheevaPlug support.

- The device is based on Marvell 88F6281 system on chip.
- More info about the platform at http://www.plugcomputer.org

- To build the FreeBSD kernel:
make buildkernel TARGET_ARCH=arm KERNCONF=SHEEVAPLUG

- Installation notes at: http://wiki.freebsd.org/FreeBSDMarvell

Submitted by: Michal Hajduk
Obtained from: Semihalf

Exclude common Kirkwood settings so they can be shared among various platforms
based on this SOC. This is a preliminary step for SheevaPlug support.

Submitted by: Michal Hajduk
Obtained from: Semihalf

Properly handle initial state of power mgmt.

Modules on Marvell SOC can be selectively PM-disabled, and we must not access
disabled devices' registers (attempt to initialize them) unconditionally, as
this leads to the system hang. This patch introduces graceful handling of the
PM state during devices init.

Submitted by: Michal Hajduk
Obtained from: Semihalf

Eliminate platform_pmap_init() to simplify Marvell bootstrap code.

Map DPCPU pages into ARM kernel VA space.

DPCPU area was not properly mapped into kernel VA space, which caused page
fault on the first DPCPU access. This patch fixes the problem by mapping DPCPU
area into kernel VA space.

Submitted by: Michal Hajduk, Piotr Ziecik
Reviewed by: cognet, stas
Approved by: re (kib)
Obtained from: Semihalf

Enable all populated TWSI (I2C) controllers on Marvell SOCs.

Obtained from: Semihalf

Introduce ata(4) support for Marvell integrated SATA controllers (found on
88F5xxx, 88F6xxx and MV78xxx system on chip devices).

Reviewed by: stas
Obtained from: Semihalf

Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
PCPU_*. Requires only one extra instruction more than PCPU_* and is
virtually the same as __thread for builtin and much faster for shared
objects. DPCPU variables can be initialized when defined.
- Modules are supported by relocating the module's per-cpu linker set
over space reserved in the kernel. Modules may fail to load if there
is insufficient space available.
- Track space available for modules with a one-off extent allocator.
Free may block for memory to allocate space for an extent.

Reviewed by: jhb, rwatson, kan, sam, grehan, marius, marcel, stas

Move the memory layout definitions and logic from mvreg.h to mvwin.h
so that it isn't exposured unless needed. In particular this means
that it's easier to tune the memory layout based on board details.
While here, remove inclusion of <machine/intr.h> from mvreg.h. This
also contains exposure to SoC specifics in MI drivers, because NIRQ
depends on the SoC.

strict kobj signatures: number of fixes for arm architecture

no functional changes should result

Reviewed by: imp, current@
Approved by: jhb (mentor)

Pass the previously returned IRQ back to arm_get_next_irq() so that
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.

Obtained from: Juniper Networks, Inc.

Adjust Marvell Discovery (MV78xxx) support to recognize newest chip revisions,
handle Z0 revision (early silicon) explicitly due to its quirks.

Obtained from: Marvell, Semihalf

Fix path and config name for ehci_mbus.c

Include Marvell EHCI HC driver for USB2.

Check PCIE link status before accessing the bus.

Some 88F5182-based systems (Linkstation) have problems when PCIE is
accessed without any peripherals present.

Rename Marvell ARM CPU specific file according to r186933.

Improve Marvell SOCs PCI/PCIE driver.

- Provide dedicated rmans for MEM and IO resources.

- Convert PCI IRQ routing info into a table (from callback approach), provide
config data for alternative DB- boards.

- Fix a wrong boundary check error in pcib_mbus_init_bar()

Obtained from: Semihalf

Improve and extend Marvell SOCs platform code.

- Allow for setting per platform MPP/GPIO configuration in the kernel, so
that we can override all settings firmware might set.

- Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR.

- Improve handling of USB controllers so that all port are available on the
given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of
USB decode windows set-up.

- Other minor fixes and cosmetics.

Obtained from: Semihalf

Minor style(9) corrections.

Adjust Marvell SOC support for A0 chip revision.

- Clean up TCLK handling so that it's dynamically recognized depending on
registers settings or chip version/revision. Update registers definitions.

- Teach SOC ident routine about A0 (initial silicon version for general
audience)

Obtained from: Marvell, Semihalf

Avoid confusion and adjust link address range of Marvell Orion kernel so it is
the same as for Kirkwood and Discovery.

Fix configuration of the PCI bridge. This got omitted in the initial import of
this code.

- Fix spelling error in comments.

PR: arm/128891
Submitted by: Pavel Pankov <pankov_p@mail.ru>
Approved by: kib (mentor)

Improve error handling in pcib_mbus_identify().

Improve style(9) and other cosmetics in Marvell SOCs code.

Fix off-by-one error in mbus_attach().

PCI/PCI-Express support for Marvell systems.

Obtained from: Marvell, Semihalf

Auto-size kernel page tables allocation on Marvell systems.

This allows mini dumps to fully work for these platforms.

Obtained from: Juniper Networks, Semihalf

Introduce basic support for Marvell families of system-on-chip ARM devices:

* Orion
- 88F5181
- 88F5182
- 88F5281

* Kirkwood
- 88F6281

* Discovery
- MV78100

The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:

* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART

Other peripherals drivers will be introduced separately.

Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf