| machdep.c (206716) | machdep.c (206717) |
|---|---|
| 1 /* $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $ */ 2/* tracked to 1.38 */ 3/* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by --- 26 unchanged lines hidden (view full) --- 35 * SUCH DAMAGE. 36 * 37 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 38 * Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp 39 * JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49 40 */ 41 42#include <sys/cdefs.h> | 1 /* $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $ */ 2/* tracked to 1.38 */ 3/* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by --- 26 unchanged lines hidden (view full) --- 35 * SUCH DAMAGE. 36 * 37 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 38 * Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp 39 * JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49 40 */ 41 42#include <sys/cdefs.h> |
| 43__FBSDID("$FreeBSD: head/sys/mips/mips/machdep.c 206716 2010-04-17 00:05:22Z jmallett $"); | 43__FBSDID("$FreeBSD: head/sys/mips/mips/machdep.c 206717 2010-04-17 01:17:31Z jmallett $"); |
| 44 45#include "opt_cputype.h" 46#include "opt_ddb.h" 47#include "opt_md.h" 48#include "opt_msgbuf.h" 49 50#include <sys/param.h> 51#include <sys/proc.h> --- 313 unchanged lines hidden (view full) --- 365 mips_icache_sync_all(); 366 mips_dcache_wbinv_all(); 367 368 /* 369 * Mask all interrupts. Each interrupt will be enabled 370 * when handler is installed for it 371 */ 372 set_intr_mask(ALL_INT_MASK); | 44 45#include "opt_cputype.h" 46#include "opt_ddb.h" 47#include "opt_md.h" 48#include "opt_msgbuf.h" 49 50#include <sys/param.h> 51#include <sys/proc.h> --- 313 unchanged lines hidden (view full) --- 365 mips_icache_sync_all(); 366 mips_dcache_wbinv_all(); 367 368 /* 369 * Mask all interrupts. Each interrupt will be enabled 370 * when handler is installed for it 371 */ 372 set_intr_mask(ALL_INT_MASK); |
| 373 enableintr(); | 373 intr_enable(); |
| 374 375 /* Clear BEV in SR so we start handling our own exceptions */ | 374 375 /* Clear BEV in SR so we start handling our own exceptions */ |
| 376 mips_cp0_status_write(mips_cp0_status_read() & ~SR_BOOT_EXC_VEC); 377 | 376 mips_wr_status(mips_rd_status() & ~SR_BOOT_EXC_VEC); |
| 378} 379 380/* 381 * Fix kernel_kseg0_end address in case trampoline placed debug sympols 382 * data there 383 */ 384void 385mips_postboot_fixup(void) --- 80 unchanged lines hidden (view full) --- 466 467void 468spinlock_enter(void) 469{ 470 struct thread *td; 471 472 td = curthread; 473 if (td->td_md.md_spinlock_count == 0) | 377} 378 379/* 380 * Fix kernel_kseg0_end address in case trampoline placed debug sympols 381 * data there 382 */ 383void 384mips_postboot_fixup(void) --- 80 unchanged lines hidden (view full) --- 465 466void 467spinlock_enter(void) 468{ 469 struct thread *td; 470 471 td = curthread; 472 if (td->td_md.md_spinlock_count == 0) |
| 474 td->td_md.md_saved_intr = disableintr(); | 473 td->td_md.md_saved_intr = intr_disable(); |
| 475 td->td_md.md_spinlock_count++; 476 critical_enter(); 477} 478 479void 480spinlock_exit(void) 481{ 482 struct thread *td; 483 484 td = curthread; 485 critical_exit(); 486 td->td_md.md_spinlock_count--; 487 if (td->td_md.md_spinlock_count == 0) | 474 td->td_md.md_spinlock_count++; 475 critical_enter(); 476} 477 478void 479spinlock_exit(void) 480{ 481 struct thread *td; 482 483 td = curthread; 484 critical_exit(); 485 td->td_md.md_spinlock_count--; 486 if (td->td_md.md_spinlock_count == 0) |
| 488 restoreintr(td->td_md.md_saved_intr); | 487 intr_restore(td->td_md.md_saved_intr); |
| 489} 490 | 488} 489 |
| 491u_int32_t 492get_cyclecount(void) 493{ 494 u_int32_t count; 495 496 mfc0_macro(count, 9); 497 return (count); 498} 499 | |
| 500/* 501 * call platform specific code to halt (until next interrupt) for the idle loop 502 */ 503void 504cpu_idle(int busy) 505{ | 490/* 491 * call platform specific code to halt (until next interrupt) for the idle loop 492 */ 493void 494cpu_idle(int busy) 495{ |
| 506 if (mips_cp0_status_read() & SR_INT_ENAB) | 496 if (mips_rd_status() & SR_INT_ENAB) |
| 507 __asm __volatile ("wait"); 508 else 509 panic("ints disabled in idleproc!"); 510} 511 512void 513dumpsys(struct dumperinfo *di __unused) 514{ --- 23 unchanged lines hidden --- | 497 __asm __volatile ("wait"); 498 else 499 panic("ints disabled in idleproc!"); 500} 501 502void 503dumpsys(struct dumperinfo *di __unused) 504{ --- 23 unchanged lines hidden --- |