| SIFixSGPRCopies.cpp (263508) | SIFixSGPRCopies.cpp (266715) |
|---|---|
| 1//===-- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 173 unchanged lines hidden (view full) --- 182 unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); 183 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); 184 const TargetRegisterClass *SrcRC; 185 186 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || 187 DstRC == &AMDGPU::M0RegRegClass) 188 return false; 189 | 1//===-- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 173 unchanged lines hidden (view full) --- 182 unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); 183 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); 184 const TargetRegisterClass *SrcRC; 185 186 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || 187 DstRC == &AMDGPU::M0RegRegClass) 188 return false; 189 |
| 190 SrcRC = inferRegClassFromDef(TRI, MRI, SrcReg, SrcSubReg); | 190 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg); |
| 191 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); 192} 193 194bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { 195 MachineRegisterInfo &MRI = MF.getRegInfo(); 196 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( 197 MF.getTarget().getRegisterInfo()); 198 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( --- 65 unchanged lines hidden --- | 191 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); 192} 193 194bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { 195 MachineRegisterInfo &MRI = MF.getRegInfo(); 196 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( 197 MF.getTarget().getRegisterInfo()); 198 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( --- 65 unchanged lines hidden --- |