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AMDGPUInstructions.td (263508) AMDGPUInstructions.td (266715)
1//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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383// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
384class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
385 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
386 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
387>;
388
389// Bitfield extract patterns
390
1//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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383// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
384class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
385 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
386 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
387>;
388
389// Bitfield extract patterns
390
391/*
392
393XXX: The BFE pattern is not working correctly because the XForm is not being
394applied.
395
391def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
392def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
393 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
394
395class BFEPattern <Instruction BFE> : Pat <
396 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
397 (BFE $x, $y, $z)
398>;
399
396def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
397def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
398 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
399
400class BFEPattern <Instruction BFE> : Pat <
401 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
402 (BFE $x, $y, $z)
403>;
404
405*/
406
400// rotr pattern
401class ROTRPattern <Instruction BIT_ALIGN> : Pat <
402 (rotr i32:$src0, i32:$src1),
403 (BIT_ALIGN $src0, $src0, $src1)
404>;
405
406// 24-bit arithmetic patterns
407def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;

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407// rotr pattern
408class ROTRPattern <Instruction BIT_ALIGN> : Pat <
409 (rotr i32:$src0, i32:$src1),
410 (BIT_ALIGN $src0, $src0, $src1)
411>;
412
413// 24-bit arithmetic patterns
414def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;

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